ORSPI4 datasheet(19/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Programmable Logic Features

• High-performance programmable logic:

– 0.16 µm, 7-level metal technology.

– Internal performance of >250 MHz.

– Over 600K usable system gates.

– Meets multiple I/O interface standards.

– 1.5 V operation (30% less power than 1.8 V operation), translates to greater performance.

• Traditional I/O selections:

– LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os.

– Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.

– Individually programmable drive capability:

24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.

– Two slew rates supported (fast and slew-limited).

– Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time.

– Fast open-drain drive capability.

– Capability to register 3-state enable signal.

– Off-chip clock drive capability.

– Two-input function generator in output path.

• New programmable high-speed I/O:

– Single-ended: GTL, GTL+, PECL, SSTL3/2 (Class I and II), HSTL (Class I, III, IV), ZBT, and DDR.

– Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable, (on/off) internal parallel termination (100

Ω) is also supported for these I/Os.

•New capability to (de)multiplex I/O signals:

– New DDR on both input and output at rates up to 350 MHz (700 Mbits/s effective rate).

– New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).

• Enhanced twin-quad Programmable Function Unit (PFU):

– Eight 16-bit Look-Up Tables (LUTs) per PFU.

– Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen-

dently, plus one extra for arithmetic operations.

– New register control in each PFU has two independent programmable clocks, clock enables, local

SET/RESET, and data selects.

– New LUT structure allows ﬂexible combinations of LUT4, LUT5, new LUT6, 4

→ 1 MUX, new

→ 1 MUX, and ripple mode arithmetic functions in the same PFU.

– 32 x 4 RAM per PFU, conﬁgurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in

only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers.

– Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast

internal routing which reduces routing congestion and improves speed.

– Flexible fast access to PFU inputs from routing.

– Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func-

tions, with the option to register the PFU carry-out.

• Abundant high-speed buffered and non-buffered routing resources provide 2x average speed improvements over

previous architectures.

• Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in

faster routing times with predictable and efﬁcient performance.

• SLIC provides eight 3-state buffers, up to a 10-bit decoder, and

PAL™-like AND-OR-Invert (AOI) in each pro-

grammable logic cell.

• New 200 MHz embedded quad-port RAM blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables.

Each embedded RAM block can be conﬁgured as:

– 1—512 x 18 (quad-port, two read/two write) with optional built in arbitration.

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