ORSPI4 datasheet(77/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

• Monitors for continuous alignment (if more than a programmable number of DIP-4 parity errors exist, there may

be an alignment problem). In the event of DIP-4 parity errors, instructs the status block to send status framing

pattern “11” on the receive SPI4 status bus.

• Removes idle/training words.

• Extracts link address and SOP, EOP and valid packet (no error) signals.

Receive DPRAMs

There are four DPRAMs referred to as banks 0, 1, 2 and 3. Each bank has a 32-bit data interface to the FPGA.

Each DPRAM has its own individual read enable and read clock allowing it to be read by the FPGA application

independently.

Every DPRAM bank is conﬁgured by software to operate in one of 32-bit, 64-bit or 128-bit mode. Every DPRAM

bank is also conﬁgured to contain 1, 2, 4 or 8 virtual FIFOs. The user determines the number of FIFOs depending

on the number of ports and buffer requirements for the ports as required by a given application. The programming

of a DPRAM bank in 32-bit, 64-bit or 128-bit mode and programming of the number of virtual FIFOs within a

DPRAM bank is done through software as shown in Table 18. Note that in 64-bit mode, DPRAMs 0 and 1 have to

be conﬁgured identically. The combined DPRAM pair is referred to as DPRAM “0”. Similarly DPRAM pairs 2 and 3

have to be conﬁgured identically. This combined DPRAM pair is referred to as DPRAM “2”. In 128-bit mode, all

DPRAMs have to be conﬁgured identically. The combined DPRAM banks are collectively referred to as DPRAM “0”.

The aggregation modes can be used in ﬁve possible combinations as shown in Table 16. The size of the embedded

data and control FIFOs for each mode is shown in Table 17. The user accesses a virtual FIFO using the 3-bit FIFO

read address (refer to Table 12, Table 13, and Table 14) from the FPGA. Table 15 shows the indexed partition

based upon the conﬁgured DPRAM partitioning and aggregation mode.

In 32-bit operating mode, the user always reads data as four 32-bit word bursts (plus one additional clock cycle to

read the port ID) unless an EOP is received. If an EOP occurs and the ASTOP_ON_EOPj (j=0,1,2,3) or

BSTOP_ON_EOPj is ‘0’, the core will cease transmission of the remaining words in the burst and start transferring

the next set of data. For example, if the EOP happens in the second word of a 4-word burst, the core will not pro-

vide the remaining two words. Instead, it will start bursting the next set of data. The exception is when the

ASTOP_ON_EOPj (j=0,1,2,3) or BSTOP_ON_EOPj is asserted. When this signal is ‘1’, the core will pause for 2

clock cycles after an EOP. The byte enables (SPIA_RX32_BE_j) are set to ‘0’ indicating that the read data is not

valid.

Table 15. FIFO Address Based on Programmed Virtual FIFOs

FIFO Address

(from FPGA)

Description

XXX

Ignored when a DPRAM is conﬁgured to support only one virtual FIFO

000

Selects FIFO 0 when DPRAM is conﬁgured to support 2, 4 or 8 virtual FIFOs

001

Selects FIFO 1 when DPRAM is conﬁgured to support 2, 4 or 8 virtual FIFOs

010

Selects FIFO 2 when DPRAM is conﬁgured to support 4 or 8 virtual FIFOs

011

Selects FIFO 3 when DPRAM is conﬁgured to support 4 or 8 virtual FIFOs

100

Selects FIFO 4 when DPRAM is conﬁgured to support 8 virtual FIFOs

101

Selects FIFO 5 when DPRAM is conﬁgured to support 8 virtual FIFOs

110

Selects FIFO 6 when DPRAM is conﬁgured to support 8 virtual FIFOs

111

Selects FIFO 7 when DPRAM is conﬁgured to support 8 virtual FIFOs

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