ORSPI4 datasheet(67/263 Pages) LATTICE

67 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 28. Data: ATX_PORTID[7:0], BTX_PORTID[7:0], ATX_STAT[1:0], BTX_STAT[1:0], ABURST_VAL[3:0],

BBURST_VAL[3:0]

Clock: ATREFCLK, BTREFCLK

SPI4 Transmit Software Interface

The SPI4 transmit interface is conﬁgurable through a System Bus interface incorporated within the embedded core.

The user can gain access to the System Bus either through the integrated MPI interface, or through FPGA

resources using the System Bus Master/Slave interface. Please refer to the appropriate Lattice Semiconductor

data sheets and application notes for more information regarding these interfaces.

The Transmit SPI4 interface logic incorporates many conﬁgurable control registers, as well as interrupt and status

registers to monitor SPI4 performance. Table 47 provides a memory map and description of each register within

the Transmit portion of the SPI4 embedded core.

Special Operating Modes

Quarter-Rate Mode

The ORSPI4 SPI4 TX interface is designed to operate at data rates much lower than 622 Mbps. Even though the

OIF standard speciﬁes a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who wish to

use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ethernet, etc.).

To enable this low speed mode, user should set the software register bit SPI4_QUARTER_RATE (Address 30915

in SPIA and 30A15 in SPIB) to ‘1’. This supports data rates in the range of 100 - 200 Mbps. Note that the normal

operating modes 32-bit, 64-bit and 128-bit are independent of the quarter-rate mode. In quarter-rate mode, the

transmit PLL is held in reset by setting the MRESET hardware pin to ‘1’. The PLL bypass mode is enabled by set-

ting the BYPASS pin to ‘1’ which causes the SPI[A,B]_TREFCLK_X8 clock from the FPGA to be used as the trans-

mit reference clock. It must be two- times the desired Transmit SPI4 line clock rate. When not operating the

Transmit SPI4 core in quarter-rate mode, this signal should be tied off. Ex: For a 100 MHz Transmit SPI4 line clock,

SPIA_TREFCLK_X8 from the FPGA must be 200 MHz.

3.5/0.5 ns

4.0/1.0 ns

5.4 / 2.1 ns

FPGA

Embedded Core

1.36/ 0.47 ns

Delay

(includes ck to Q)

Clock Insertion

TREFCLK

(from off-chip)

ATREFCK_F

BTREFCLK_F

Delay = 6.8 / 2.4 ns

NOTE: Delays represent average max/min values, not absolute values

Actual delay values are used by

ispLEVER

Buffer

Delay

Clock Buffer Delay

Relative to Data

ORSPI4 Fiches technique(PDF) 67 Page - Lattice Semiconductor

ORSPI4 Fiches technique(HTML) 67 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL