ORSPI4 datasheet(25/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

The bit ordering in the data format in the 32-bit aggregation mode is shown in Figure 7. In 32-bit mode, data trans-

fers are done in 4-word bursts with the exception of an EOP. As shown in the ﬁgure, SOP is always aligned to the

most signiﬁcant 32-bit word, Word 0 of a 4-word burst. The ﬁrst byte of a packet is always Word 0. The SOP indica-

tor is high during Word 0. EOP can be any byte within the 32-bit word. The last valid byte enable within a 32-bit

word indicates the end of packet. The EOP signal can be high during Word 0, Word 1, Word 2 or Word 3. It should

be used in conjunction with the byte enables to determine the last byte in that data transfer. If data transfers do not

end on Word 3, then the burst is terminated and Word 0 of the next burst is sent to the user. For example, if EOP

occurs during Word 2, Word 3 will be discarded and Word 0 of the next word will be sent to the user.

Figure 7. Byte and Bit Ordering in 32-Bit Operating Mode

The bit ordering in the data format in the 64-bit aggregation mode is shown in Figure 8. In 64-bit mode, data trans-

fers are done in 2-word bursts with the exception of an EOP. As shown in the ﬁgure, SOP is always aligned to the

most signiﬁcant 64-bit Word 0 of a 2-word burst. The ﬁrst byte of a packet is always Word 0. The SOP indicator is

high during word Word 0.

Figure 8. Byte and Bit Ordering in 64-Bit Mode

Byte 0 Byte 1 Byte 2 Byte 3

Byte 0 Byte 1Byte 2 Byte 3

Byte 0 Byte 1 Byte 2 Byte 3

Byte 0 Byte 1Byte 2 Byte 3

Word 3

SPI[A,B]_RX32_DATA_j[31:0]

Clock 1

Clock 2

Clock 3

Clock 4

Word 2

Word 1

Word 0

SPI[A,B]_RX32_SOP_j

127

95 63

DPRAM

FPGA

W 0

W 2 W 3

W 1

Time

Byte 0 is the SOP

SPI[A,B]_TX32_DATA_j[31:0]

SPI[A,B]_RX32_SOP_j

Byte4 Byte 5Byte 6 Byte 7

39 32

Byte 0 Byte 1Byte 2 Byte 3

31 23

Byte 4Byte 5Byte 6 Byte 7

39 32

Byte 0 Byte 1Byte 2 Byte 3

Clock 1

Clock 2

Word 1

Word 0

SPI[A,B]_RX64_SOP_j

127

95 63

DPRAM

FPGA

Word 1

Word 0

Time

SPI[A,B]_RX64_DATA_j[63:0]

SPI[A,B]_TX64_DATA_j[63:0]

SPI[A,B]_TX64_SOP_j

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