ORSPI4 datasheet(36/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

SPIA_TX64_LINK_DIS_0

FPGA

→ Core Link disable control signal. When asserted to a logic '1', the AMA will cease

polling from a DPRAM. All ports associated with a disabled DPRAM will

remain unserviced until the control signal is deasserted. The AMA will send

IDLE data across the SPI4 link. If the application continues to write data to

that port FIFO, it will eventually ﬁll and provide proper FIFO ﬁll status to the

application.

SPIA_TX64_CLK_0

FPGA

→ Core Transmit write reference clock. The clocks across the different transmit

interfaces are independent from each other, and are not required to be syn-

chronous to each other.

SPIA_TX64_FIFO_FULL_0

Core

→FPGA FIFO full status. The status is given in response to the assertion of any

valid address on the SPIA_TX64_ADDR_1[2:0] bus. This signal will be

asserted to a logic '1' when the current FIFO partition has crossed the con-

ﬁgured ﬁll level within the partition.

SPIA_TX64_ADDR_1[2:0]

FPGA

→ Core Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum

of eight partitions. When operating in 64-bit mode, each partition will be 2x

the depth of the corresponding partition in 32-bit mode. More than one port

can be conﬁgured to share a virtual FIFO partition.

SPIA_TX64_DATA_1[63:0]

FPGA

→ Core User Write data. Two writes are required in order to complete an entire 128-

bit line. All writes must occur in two write bursts, unless an EOP occurs.

SPIA_TX64_BE_1[7:0]

FPGA

→ Core Byte enables indicating which bytes within the 64-bit word are valid.

Bit[7]-Byte enable for SPIA_TX64_DATA_0[63:56]

Bit[6]-Byte enable for SPIA_TX64_DATA_0[55:48]

Bit[5]-Byte enable for SPIA_TX64_DATA_0[47:40]

Bit[4]-Byte enable for SPIA_TX64_DATA_0[39:32]

Bit[3]-Byte enable for SPIA_TX64_DATA_0[31:24]

Bit[2]-Byte enable for SPIA_TX64_DATA_0[23:16]

Bit[1]-Byte enable for SPIA_TX64_DATA_0[15:8]

Bit[0]-Byte enable for SPIA_TX64_DATA_0[7:0]

If no BE bits are asserted for a particular location within the DPRAM, data

will be dropped and no write to the DPRAM will occur.

According to the SPI-4.2 speciﬁcation, the BE bits must be asserted for all

but the last transfer, where an End of Packet or Error may occur. The valid

combinations of BE are as follows:

BE[7:0] = 11111111--indicates all eight bytes contain valid user data. If an

EOP is present, it resides within the eighth byte.

BE[7:0] = 11111110--indicates seven bytes are valid. EOP occurs in sev-

enth Byte.

BE[7:0] = 11111100--indicates six bytes are valid. EOP occurs in sixth

Byte.

BE[7:0] = 11111000--indicates ﬁve byte is valid. EOP occurs in ﬁfth Byte.

BE[7:0] = 11110000--indicates four bytes are valid. EOP occurs in fourth

Byte.

BE[7:0] = 11100000--indicates three bytes are valid. EOP occurs in third

Byte.

BE[7:0] = 11000000--indicates two bytes are valid. EOP occurs in second

Byte.

BE[7:0] = 10000000--indicates one byte is valid. EOP occurs in ﬁrst Byte.

SPIA_TX64_SOP_1

FPGA

→ Core

Start of Packet indicator. A '1' indicates the start of packet for a particular

port. When operating in 64-bit mode, the SOP indicator must be asserted

coincident with the ﬁrst write per address line within the FIFO partition.

SPIA_TX64_EOP_1

FPGA

→ Core

End of Packet indicator. A '1' indicates the end of packet for a particular

port. The EOP may be asserted on either write per address line within the

FIFO partition.

Table 3. SPIA Core Transmit FPGA Interface in 64-Bit Mode (Continued)

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

Note: For SPIB replace A with B

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