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ORCA ORSPI4 Data Sheet

synchronous DDR clock (RDCLK). The 16-bit data bus and control signal are DDR with respect to RDCLK. The

incoming data is deserialized to a 128-bit format and the control information is converted to an 8-bit format. Deseri-

alized data, control signals and a low-speed clock, derived from the high-speed RDCLK, are forwarded to the pro-

tocol (RDP) block.

The RDI block alignment logic detects training patterns and perform dynamic alignment of the incoming data. For

low speed incoming data at rates up to 700 Mbits/s, static alignment can be chosen through a programmable con-

trol bit. The low speed mode is described in a later section. At speeds above 700 Mb/s (350 MHz), however, it

becomes necessary to use dynamic alignment. Skews of up to ± one clock period can be compensated for by the

dynamic alignment logic, which chooses the best phase of the receive clock, out of 16 possibilities, to center each

data bit for the best possible setup/hold margin. The receive dynamic alignment logic periodically samples the data

to verify that data can be transferred reliably as temperature and voltage levels in the system vary. It then makes

appropriate adjustments as needed.

The output from the RDI block is the low speed 128-bit data bus and 8-bit control bus along with a low speed clock

which is 1/4th the rate of the SPI4 receive clock RDCLK.

The ORSPI4 receive high-speed interface also supports static data capture as shown in Figure 30. As shown in the

ﬁgure, the key difference that exists between the clock and data paths is the delay line in the clock path. The high-

speed loopback works in both static and dynamic alignment modes. The delay line circuit is a series of buffers with

programmable stages that are controlled through two signals from the FPGA - SPI_DATM_A (SPIA) or

SPI_DATM_B (SPIB) and SPI_DLYTAP_A[2:0] (SPIA) or SPI_DLYTAP_B[2:0] (SPIB). The object of having pro-

grammable delay stages is to delay RDCLK appropriately so that both its rising and falling edges hit the data eye

with sufﬁcient setup and hold margin for data capture. Various delay settings allow the data to be centered vs. the

clock for the best setup and hold margin. For details on programming the ORSPI4 receiver in static and dynamic

capture modes, refer to the section “Static Capture Operating Mode”.

Figure 30. Static Data Capture

RDP Block

The SPI4 Receive Data Protocol (RDP) block receives data from RDI block and is responsible for decoding the in-

band control information while preserving wire-speed throughput. It passes both data and control information, such

as link address, SOP, EOP and error, to the Receive DPRAMs.

The RDP block also parses the control words embedded within the incoming data. Using this control information, it

performs the following functions:

• Checks DIP-4 parity

[A,B]RDAT[15:0]

[A,B]RDCLK

LVDS

Buffers

LVDS

Buffers

From Transmit Blocks

SPI4_LOOPBK_HS

Dynamic

Static

data

clock

data

clock

Delay

SPI_DLYTAP_[A,B][2:0]

SPI_DATM_[A,B]

(Controls from

FPGA)

Line

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