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ORCA ORSPI4 Data Sheet

based on the empty status signals presented from the FIFOs. The user can select a 32-bit, 64-bit or 128-bit wide

FIFO interface depending on the FPGA design requirements.

There are two SPI4 cores in the ORSPI4 device. They are referenced in the document as SPIA and SPIB respec-

tively.

ORSPI4 Receive Embedded Core/FPGA Interface Description

ORSPI4 Receive I/O Modes

The FPGA interface I/Os to the ORSPI4 logic block vary depending on the operating modes. There are three main

user operating modes:

• 32-bit operating mode: Each of the four DPRAMs can be conﬁgured with a 32-bit user data plus controls across

the FPGA interface. This mode is particularly useful if the user is aggregating multiple 32-bit interfaces into a sin-

gle SPI4 interface.

• 64-bit operating mode: A DPRAM pair can be conﬁgured with 64-bit user data bus plus controls across the FPGA

interface. Two such DPRAM pairs are available. More ﬂexibility is provided by conﬁguring one pair of DPRAM

banks in 64-bit mode and the remaining two banks in 32-bit mode.

• 128-bit operating mode: All four DPRAM banks are aggregated into a single FIFO with a 128-bit user data inter-

face.

Several other features are:

• Ability to pause for two clock cycles when an EOP is detected using the ASTOP_ON_EOP (SPIA) or

BSTOP_ON_EOP (SPIB) control signal. Please refer to the timing diagrams for detailed information.

Table 12 lists I/Os for SPIA core only. They are identical in the SPIB core as well.

Table 12. SPIA Core Receive FPGA Interface in 32-Bit Mode

DPRAM

FPGA Interface I/Os

Direction

From/To

Description

SPIA_RX32_ADDR_0[2:0]

FPGA

→ Core FIFO read address.

SPIA_RX32_DATA_0[31:0]

Core

→FPGA FIFO read data.

SPIA_RX32_BE_0[3:0]

Core

→FPGA Byte enables

Bit 3 - Byte enable for SPIA_RX32_DATA_0[31:24]

Bit 2 - Byte enable for SPIA_RX32_DATA_0[23:16]

Bit 1 - Byte enable for SPIA_RX32_DATA_0[15:8]

Bit 0 - Byte enable for SPIA_RX32_DATA_0[7:0]

SPIA_RX32_CTL_0

Core

→FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX32_DATA_0 bus contains

the port ID.

SPIA_RX32_SOP_0

Core

→FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.

SPIA_RX32_EOP_0

Core

→FPGA End of Packet Indicator. A ‘1’ indicates end of packet.

SPIA_RX32_ERR_0

Core

→FPGA Error. A ‘1’ indicates an error in the current word.

SPIA_RX32_FIFO_EMPTY_0 Core

→FPGA FIFO Empty ﬂag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0]

software register bit in address 0x30920. When this bit is set to ‘0’, (default)

the empty ﬂag indicates truly empty.

When this bit is set to ‘1’, the empty ﬂag indicates that the FIFO is 1/4 full -

ASTOP_ON_EOP0

FPGA

→ Core Timing control for handling end of packet.

SPIA_RX32_CLK_0

FPGA

→ Core FIFO read clock.

SPIA_RX32_RD_0

FPGA

→ Core FIFO read enable.

Note: For SPIB replace A with B

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