ORSPI4 datasheet(98/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

Figure 43. Far End Loopback

Far End Loopback Setup

The following three step procedure will set up the ORSPI4 into far end loopback mode:

Set up the external connections to the ORSPI4 such that the RDAT, RDCLK, and RCTL SPI-4 ports are all

receiving signals. (If in quarter rate mode, the FPGA-sourced clock reference signal SPI[A,B]_TREFCLK_X8

must be supplied at twice the rate as the applied [A,B]RDCLK SPI-4 port clock.

Conﬁgure the appropriate ORSPI4 register as shown in Table 25. Note that either choice of LVTTL or LVDS for

status buffer is acceptable for far end loopback, although the choice will affect the status port timing. Also note

that bits 6 and 7 (TX_FORCE_DIP4_ERR and RX_FORCE_DIP2_ERR) do not affect the operation of far end

loopback.

Reset the appropriate SPI4 block with control signal FPGA_RESET_S4[A,B].

TDAT[15:0]

TCTL

TDCLK

SPI4 I/F

TDO

TREFCLK

TSI

TSTAT[1:0]

TSCLK

RDAT[15:0]

RCTL

RDCLK

RDI

RSO

RSTAT[1:0]

RSCLK

TDP

128-bit

data+ctl

TSP

DPRAMs

+ associated

logic

Port write

Sequencer

FPGA

RDP

RSP

DPRAMs

+ associated

logic

Port Status

Sequencer

clk

128-bit

data+ctl

clk

Embedded Core

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