STLC5460 datasheet(12/54 Pages) STMICROELECTRONICS

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CONFIGURATION REGISTER DESCRIPTION

Initialisation and Identification Register (IIR)

RBS

RST

After Reset 3F (H)

T1/T0 Test functions

Description

Normal State

Command Memory or Auxiliary Auto Reset.

If CM = 1 (Bit of Command Register):

the six lower bits of command Register and the eight bits of Source Register are stored

into each address of command Memory.

If CM = 0 (Bit of Command Register) :

the eight bits of Source Register are stored into each address of Monitor Auxililary

Memory and the six lower bits of Source Register are stored intoCommand/Indicate

Auxilliary Memory.

The 16 C/I and Monitor channels are ready to transmit and to receive data.After

AutoReset, BUSY and T0 goes to ”0”.

Auto Test. This function is reserved for manufacturer.

- The Pseudo Random Sequence generator is connected instead of Insert A Register and

Pseudo Random Sequence Analyzer is connected instead of Extract A Register.

- The Command Memory is loaded thanks to a special algorithm in order to switch the

sequence provided by the generator into TSO of PCMO, then the contents of TSO of

PCMO into TS1 of PCMO, then the contents of TS1 of PCMO into TS2 of PCMO and

so on.

Finally, the contents of TS31 of MUX1 are taken into account by the Pseudo Random

Sequence Analyzer.After loading Command Memory, 193 switching are set up in real

time.The analyzer receives the Pseudo Random Sequence from the generator after

switching.

If LP = 1, the loopback is internal.

If LP = 0, an external loopback must be performed. So, Command Memory and Data

Memory can be checked in the same time.

Reserved. Initialise CM so that the content of each input Time Slot t of input multiplex m is

switched to output Time Slot t of output multiplex m

RBS

RBS = 0. The 16 first main registers are selected (0 to 15).

RST

Reset Soft.

the programmable registers are reset.

V3/V0

these bits are fixed at 0

COMPARISON REGISTER (COMP)

NEWE

TIM

CP6

CP5

CP4

CP3

CP2

CP1

After Reset 00 (H)

NEWE

New EXTRACT.

When NEWE = 1, EXT interrupt is generated only if a new word is loaded into

EXTRACT Registers (A or B).

TIM

Timer, associated to INS of INT Register and to TIMO/1 of CPOF register.

TIM = 1

TIM0/1 bits of CPOF register are taken into account

TIM = 0

an interrupt is generated each 125

µs.

STLC5460

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