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AD9516-2/PCBZ Fiches technique(PDF) 17 Page - Analog Devices |
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AD9516-2/PCBZ Fiches technique(HTML) 17 Page - Analog Devices |
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17 / 84 page ![]() AD9516-2 Rev. 0 | Page 17 of 84 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VS REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS VS CLK CLK NC SCLK NC = NO CONNECT OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) GND OUT2 OUT2 VS_LVPECL OUT3 OUT3 VS GND OUT9 (OUT9B) OUT9 (OUT9A) OUT8 (OUT8B) OUT8 (OUT8A) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9516-2 TOP VIEW (Not to Scale) LVPECL LVPECL LVPECL LVPECL Figure 6. Pin Configuration Table 20. Pin Function Descriptions Pin No. Mnemonic Description 1, 11, 12, 30, 31, 32, 38, 49, 50, 51, 57, 60, 61 VS 3.3 V Power Pins. 2 REFMON Reference Monitor (Output). This pin has multiple selectable outputs; see Table 53 0x1B. 3 LD Lock Detect (Output). This pin has multiple selectable outputs; see Table 53 0x1A. 4 VCP Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. 5 CP Charge Pump (Output). Connects to external loop filter. 6 STATUS Status (Output). This pin has multiple selectable outputs; see Table 53 0x17. 7 REF_SEL Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. 8 SYNC Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. 9 LF Loop Filter (Input). Connects to VCO control voltage node internally. 10 BYPASS This pin is for bypassing the LDO to ground with a capacitor. 13 CLK Along with CLK, this is the differential input for the clock distribution section. 14 CLK Along with CLK, this is the differential input for the clock distribution section. 15, 18, 19, 20 NC No Connection. 16 SCLK Serial Control Port Data Clock Signal. 17 CS Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. 21 SDO Serial Control Port Unidirectional Serial Data Out. 22 SDIO Serial Control Port Bidirectional Serial Data In/Out. 23 RESET Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor. 24 PD Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor. 27, 41, 54 VS_LVPECL Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. 37, 44, 59, EPAD GND Ground Pins; Includes External Paddle (EPAD). 56 OUT0 LVPECL Output; One Side of a Differential LVPECL Output. |
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