AD9516-2SLASHPCBZ datasheet(36/84 Pages) AD

36 / 84 page

AD9516-2

Rev. 0 | Page 36 of 84

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,

in which case the previous equation also applies.

By using combinations of DM and FD modes, the AD9516 can

achieve values of N all the way down to N = 1. Table 28 shows

how a 10 MHz reference input may be locked to any integer

multiple of N.

Note that the same value of N may be derived in different ways,

as illustrated by the case of N = 12. The user may choose a fixed

divide mode P = 2 with B = 6, or use the dual modulus mode

2/3 with A = 0, B = 6, or use the dual modulus mode 4/5 with

A = 0, B = 3.

A and B Counters

The AD9516 B counter can be bypassed (B = 1). This B counter

bypass mode is only valid when using the prescaler in FD mode.

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.

Unlike the R-counter, an A = 0 is actually a zero. The B counter

must be ≥3 or bypassed.

The maximum input frequency to the A/B counter is reflected

in the maximum prescaler output frequency (~300 MHz)

specified in Table 2. This is the prescaler input frequency (VCO

or CLK) divided by P.

Although manual reset is not normally required, the A/B counters

have their own reset bit. A and B counters can be reset using the

shared reset bit of the R, A, and B counters. They may also be

reset through a SYNC operation.

R, A, and B Counters: SYNC Pin Reset

The R, A and B counters may also be reset simultaneously

through the SYNC pin. This function is controlled by 0x19<7:6>

(see Table 53). The SYNC pin reset is disabled by default.

R and N Divider Delays

Both the R and N dividers feature a programmable delay cell.

These delays may be enabled to allow adjustment of the phase

relationship between the PLL reference clock and the VCO or

CLK. Each delay is controlled by three bits. The total delay

range is about 1 ns. See 0x19 in Table 53.

Table 28. How a 10 MHz Reference Input May Be Locked to Any Integer Multiple of N

FREF

FVCO

Mode

Notes

P = 1, B = 1 (bypassed)

P = 2, B = 1 (bypassed)

P = 1, B = 3

P = 1, B = 4

P = 1, B = 5

P = 2, B = 3

P and P + 1 = 2 and 3, A = 0, B = 3

P and P + 1 = 2 and 3, A = 1, B = 3

P and P + 1 = 2 and 3, A = 2, B = 3

P and P + 1 = 2 and 3, A = 1, B = 4

100

P = 2, B = 5

100

P and P + 1 = 2 and 3, A = 0, B = 5

110

P and P + 1 = 2 and 3, A = 1, B = 5

120

P = 2, B = 6

120

P and P + 1 = 2 and 3, A = 0, B = 6

120

P and P + 1 = 4 and 5, A = 0, B = 3

130

P and P + 1 = 4 and 5, A = 1, B = 3

AD9516-2/PCBZ Fiches technique(PDF) 36 Page - Analog Devices

AD9516-2/PCBZ Fiches technique(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Fiches technique Télécharger

Lien URL