AD9516-2SLASHPCBZ datasheet(65/84 Pages) AD

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AD9516-2

Rev. 0 | Page 65 of 84

Reg.

Addr

(Hex) Bit(s) Name

Description

<5> <4> <3>

<2>

<1> <0>

Level or

Dynamic

Signal

Signal at LD Pin

LVL

Status of unselected reference (not available in differential

mode); active low.

LVL

Status of REF1 frequency (active low).

LVL

Status of REF2 frequency (active low).

LVL

(Status of REF1 frequency) AND (Status of REF2 frequency).

LVL

(DLD) AND (Status of selected reference) AND (Status of VCO).

LVL

Status of VCO frequency (active low).

LVL

Selected reference (low = REF2, high = REF1).

LVL

Digital lock detect (DLD); active low.

LVL

Holdover active (active low).

LVL

N/A—do not use.

<7>

VCO

Enable or disable VCO frequency monitor.

Frequency

<7> = 0; disable VCO frequency monitor.

Monitor

<7> = 1; enable VCO frequency monitor.

<6>

REF2 (REFIN) Enable or disable REF2 frequency monitor.

Frequency

<6> = 0; disable REF2 frequency monitor.

Monitor

<6> = 1; enable REF2 frequency monitor.

<5>

REF1 (REFIN)

Frequency

REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs

(as selected by differential reference mode).

Monitor

<5> = 0; disable REF1 (REFIN) frequency monitor.

<5> = 1; enable REF1 (REFIN) frequency monitor.

<4:0> REFMON Pin Select the signal that is connected to the REFMON pin.

Control

<4>

<3> <2>

<1>

<0>

Level or

Dynamic

Signal

Signal at REFMON Pin

LVL

Ground (dc).

DYN

REF1 clock (differential reference when in differential mode).

DYN

REF2 clock (N/A in differential mode).

DYN

Selected reference to PLL (differential reference when in differential

mode).

DYN

Unselected reference to PLL (not available in differential mode).

LVL

Status of selected reference (status of differential reference);

active high.

LVL

Status of unselected reference (not available in differential mode);

active high.

LVL

Status REF1 frequency (active high).

LVL

Status REF2 frequency (active high).

LVL

(Status REF1 frequency) AND (status REF2 frequency).

LVL

(DLD) AND (status of selected reference) AND (status of VCO).

LVL

Status of VCO frequency (active high).

LVL

Selected reference (low = REF1, high = REF2).

LVL

Digital lock detect (DLD); active low.

LVL

Holdover active (active high).

LVL

LD pin comparator output (active high).

LVL

VS (PLL supply).

DYN

REF1 clock (differential reference when in differential mode).

DYN

REF2 clock (not available in differential mode).

DYN

Selected reference to PLL (differential reference when in

differential mode).

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