AD9516-2SLASHPCBZ datasheet(39/84 Pages) AD

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AD9516-2

Rev. 0 | Page 39 of 84

Once in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N

divider) is reset synchronously with the charge pump leaving

high impedance state on the reference path PFD event. This

helps align the edges out of the R and N dividers for faster

settling of the PLL and to reduce frequency errors during

settling. Because the prescaler is not reset, this feature works

best when the B and R numbers are close because this results in

a smaller phase difference for the loop to settle out.

After leaving holdover, the loop then reacquires lock and the

LD pin must charge (if 0x1D<3> = 1) before it can re-enter

holdover (CP high impedance).

The holdover function always responds to the state of the

currently selected reference (0x1C). If the loop loses lock during

a reference switchover (see the Reference Switchover section),

holdover is triggered briefly until the next reference clock edge

at the PFD.

The following registers affect the internal/automatic holdover

function:

• 0x18<6:5>—lock detect counter. This changes how many

consecutive PFD cycles with edges inside the lock detect

window are required for the DLD indicator to indicate lock.

This impacts the time required before the LD pin can begin

to charge as well as the delay from the end of a holdover

event until the holdover function can be re-engaged.

• 0x18<3>—disable digital lock detect. This bit must be set to a

0 to enable the DLD circuit. Internal/automatic holdover does

not operate correctly without the DLD function enabled.

• 0x1A<5:0>—lock detect pin output select. Set this to 000100b

to put it in the current source lock detect mode if using the

LD pin comparator. Load the LD pin with a capacitor of an

appropriate value.

• 0x1D<3>—enable LD pin comparator. 1 = enable; 0 =

disable. When disabled, the holdover function always senses

the LD pin as high.

• 0x1D<1>—enable external holdover control.

• 0x1D<0> and Register 0x1D<2>—holdover function enable.

If holdover is disabled, both external and internal/automatic

holdover are disabled.

For example, to use automatic holdover with:

• Automatic reference switchover, prefer REF1.

• Digital lock detect: five PFD cycles, high range window.

• Automatic holdover using the LD pin comparator.

The following registers are set (in addition to the normal PLL

registers):

• 0x18<6:5> = 00b; lock detect counter = five cycles.

• 0x18<4> = 0b; lock detect window = high range.

• 0x18<3> = 0b; DLD normal operation.

• 0x1A<5:0> = 000100b; current source lock detect mode.

• 0x1C<4> = 1b; automatic reference switchover enabled.

• 0x1C<3> = 0b; prefer REF1.

• 0x1C<2:1> = 11b; enable REF1 and REF2 input buffers.

• 0x1D<3> = 1b; enable LD pin comparator.

• 0x1D<2> = 1b; enable the holdover function.

• 0x1D<1> = 0b; use internal/automatic holdover mode.

• 0x1D<0> = 1b; enable the holdover function.

Frequency Status Monitors

The AD9516 contains three frequency status monitors that are

used to indicate if the PLL reference (or references in the case of

single-ended mode) and the VCO have fallen below a threshold

frequency. A diagram showing their location in the PLL is

shown in Figure 52.

The PLL reference monitors have two threshold frequencies:

normal and extended (see Table 16). The reference frequency

monitor thresholds are selected in 0x1F.

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