AD9516-2SLASHPCBZ datasheet(48/84 Pages) AD

48 / 84 page

AD9516-2

Rev. 0 | Page 48 of 84

Synchronization of the outputs is executed in several ways:

• The SYNC pin is forced low and then released (manual sync).

• By setting and then resetting any one of the following three

bits: the soft sync bit (0x230<0>), the soft reset bit (0x00<5>

[mirrored]), or the distribution power-down bit (0x230<1>).

• Synchronization of the outputs can be executed as part of the

chip power-up sequence.

• The RESET pin is forced low and then released (chip reset).

• The PD pin is forced low and then released (chip power-down).

• Whenever a VCO calibration is completed, an internal SYNC

signal is automatically asserted at the beginning and released

upon the completion of a VCO calibration.

The most common way to execute the SYNC function is to use

the SYNC pin to do a manual synchronization of the outputs.

This requires a low-going signal on the SYNC pin, which is held

low and then released when synchronization is desired. The

timing of the SYNC operation is shown in Figure 55 (using

VCO divider) and Figure 56 (VCO divider not used). There is

an uncertainty of up to 1 cycle of the clock at the input to the

channel divider due to the asynchronous nature of the SYNC

signal with respect to the clock edges inside the AD9516. The

delay from the SYNC rising edge to the beginning of synchronized

output clocking is between 14 and 15 cycles of clock at the

channel divider input, plus either one cycle of the VCO divider

input (see Figure 55), or one cycle of the channel divider input

(see Figure 56), depending on whether the VCO divider is used.

Cycles are counted from the rising edge of the signal.

Another common way to execute the SYNC function is by

setting and resetting the soft SYNC bit at 0x230<0> (see Table 52

through Table 61 for details). Both setting and resetting of the

soft SYNC bit require an update all registers (0x232<0> = 1)

operation to take effect.

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 55. SYNC Timing when VCO Divider Is Used—CLK or VCO Is Input

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