AD9516-2SLASHPCBZ datasheet(74/84 Pages) AD

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AD9516-2

Rev. 0 | Page 74 of 84

Reg.

Addr

(Hex) Bit(s) Name

Description

142

<0>

OUT8 Power-Down

Power-down output (LVDS/CMOS).

<0> = 0; power on.

<0> = 1; power off.

143

<7:5> OUT9 Output Polarity

In CMOS mode, <7:5> select the output polarity of each CMOS output.

In LVDS mode, only <5> determines LVDS polarity.

<7> <6>

<5>

OUT9A (CMOS)

OUT9B (CMOS)

OUT9 (LVDS)

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

143

<4>

OUT9 CMOS B

In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.

<4> = 0; turn off the CMOS B output.

<4> = 1; turn on the CMOS B output.

143

<3>

OUT9 Select LVDS/CMOS

Select LVDS or CMOS logic levels.

<3> = 0; LVDS.

<3> = 1; CMOS.

143

<2:1> OUT9 LVDS Output Current

Set output current level in LVDS mode. This has no effect in CMOS mode.

<2> <1> Current (mA)

Recommended Termination (Ω)

1.75

100

3.5

100

5.25

143

<0>

OUT9 Power-Down

Power-down output (LVDS/CMOS).

<0> = 0; power on.

<0> = 1; power off.

Table 57. LVPECL Channel Dividers

Reg.

Addr

(Hex) Bit(s) Name

Description

190

<7:4> Divider 0 Low Cycles

Number of clock cycles of the divider input during which divider output stays low.

190

<3:0> Divider 0 High Cycles

Number of clock cycles of the divider input during which divider output stays high.

191

<7>

Divider 0 Bypass

Bypass and power down the divider; route input to divider output.

<7> = 0; use divider.

<7> = 1; bypass divider.

191

<6>

Divider 0 Nosync

Nosync.

<6> = 0; obey chip-level SYNC signal.

<6> = 1; ignore chip-level SYNC signal.

191

<5>

Divider 0 Force High

Force divider output to high. This requires that nosync also be set.

<5> = 0; divider output forced to low.

<5> = 1; divider output forced to high.

191

<4>

Divider 0 Start High

Selects clock output to start high or start low.

<4> = 0; start low.

<4> = 1; start high.

191

<3:0> Divider 0 Phase Offset

Phase offset.

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