AD9516-2SLASHPCBZ datasheet(79/84 Pages) AD

79 / 84 page

AD9516-2

Rev. 0 | Page 79 of 84

APPLICATION NOTES

USING THE AD9516 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of its

sampling clock. An ADC can be thought of as a sampling mixer,

and any noise, distortion, or timing jitter on the clock is

combined with the desired signal at the analog-to-digital

output. Clock integrity requirements scale with the analog input

frequency and resolution, with higher analog input frequency

applications at ≥14-bit resolution being the most stringent. The

theoretical SNR of an ADC is limited by the ADC resolution

and the jitter on the sampling clock. Considering an ideal ADC

of infinite resolution where the step size and quantization error

can be ignored, the available SNR can be expressed

approximately by

⎟

⎠

⎞

⎜

⎝

⎛

SNR

log

(dB)

where:

fA is the highest analog frequency being digitized.

tJ is the rms jitter on the sampling clock.

Figure 68 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA (MHz)

100

110

= 100f

200f

400f

1ps

2ps

10ps

SNR = 20log

2πfAtJ

Figure 68. SNR and ENOB vs. Analog Input Frequency

See the AN-756 application note and the AN-501 application note

at www.analog.com.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.)

The AD9516 features both LVPECL and LVDS outputs that

provide differential clock outputs, which enable clock solutions

that maximize converter SNR performance. The input

requirements of the ADC (differential or single-ended, logic

level, termination) should be considered when selecting the best

clocking/converter solution.

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9516 provide the lowest jitter

clock signals available from the AD9516. The LVPECL outputs

(because they are open emitter) require a dc termination to bias

the output transistors. The simplified equivalent circuit in

Figure 57 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin termination

is recommended, as shown in Figure 69. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the switching threshold (VS − 1.3 V).

VS_LVPECL

LVPECL

50Ω

SINGLE-ENDED

(NOT COUPLED)

VS_LVPECL

LVPECL

127Ω

83Ω

VT = VS – 1.3V

Figure 69. LVPECL Far-End Thevenin Termination

VS_LVPECL

LVPECL

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

VS_LVPECL

LVPECL

100Ω

0.1nF

200Ω

Figure 70. LVPECL with Parallel Transmission Line

LVDS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9) that

are selectable as either CMOS or LVDS level outputs. LVDS is a

differential output option that uses a current mode output stage.

The nominal current is 3.5 mA, which yields 350 mV output

swing across a 100 Ω resistor. The LVDS output meets or

exceeds all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is

shown in Figure 71.

LVDS

100Ω

DIFFERENTIAL (COUPLED)

LVDS

100Ω

Figure 71. LVDS Output Termination

See the AN-586 application note at www.analog.com for more

information on LVDS.

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