AD9516-2SLASHPCBZ datasheet(47/84 Pages) AD

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AD9516-2

Rev. 0 | Page 47 of 84

Case 1

When Φx.1 ≤ 15 and Φx.2 ≤ 15:

Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2

Case 2

When Φx.1 ≤ 15 and Φx.2 ≥ 16:

Δt = ΦX.1 × TX.1 + (ΦX.2 – 16 + MX.2 + 1) × TX.2

Case 3

When ΦX.1 ≥ 16 and ΦX.2 ≤ 15:

Δt = (ΦX.1 − 16 + MX.1 + 1) × TX.1 + ΦX.2 × TX.2

Case 4

When ΦX.1 ≥ 16 and ΦX.2 ≥ 16:

Δt =

(ΦX.1 − 16 + MX.1 + 1) × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2

Fine Delay Adjust (Divider 3 and Divider 4)

Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes

an analog delay element that can be programmed to give

variable time delays (Δt) in the clock signal at that output.

DIVIDER

X.2

DIVIDER

X.1

ΔT

OUTM

BYPASS

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

ΔT

OUTN

BYPASS

FINE DELAY

ADJUST

CMOS

LVDS

CMOS

OUTPUT

DRIVERS

CLK

VCO

DIVIDER

Figure 54. Fine Delay (OUT6 to OUT9)

The amount of delay applied to the clock signal is determined

by programming four registers per output (see Table 46).

Table 46. Setting Analog Fine Delays

OUTPUT

(LVDS/CMOS)

Ramp

Capacitors

Ramp

Current

Delay

Fraction

Delay

Bypass

OUT6

0xA1<5:3>

0xA1<2:0>

0xA2<5:0>

0xA0<0>

OUT7

0xA4<5:3>

0xA4<2:0>

0xA5<5:0>

0xA3<0>

OUT8

0xA7<5:3>

0xA7<2:0>

0xA8<5:0>

0xA6<0>

OUT9

0xAA<5:3>

0xAA<2:0>

0xAB<5:0>

0xA9<0>

Calculating the Fine Delay

The following values and equations are used to calculate the

delay of the delay block.

IRAMP (μA) = 200 × (Ramp Current + 1)

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;

001 = 2 + 1 = 3; 111 = 0 + 1 = 1.

Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286

()

1600

0.34

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛−

−

RAMP

Caps

No.

Offset

Delay Full Scale (ns) = Delay Range + Offset

Fine Delay (ns) =

Delay Range × Delay Fraction × (1/63) + Offset

Note that only delay fraction values up to 47 decimal (101111b;

0x2F) are supported.

In no case can the fine delay exceed one-half of the output clock

period. If a delay longer than half of the clock period is

attempted, the output stops clocking.

The delay function adds some jitter greater than that specified

for the nondelayed output. This means that the delay function

should be used primarily for clocking digital chips, such as

FPGA, ASIC, DUC, and DDC. An output with this delay

enabled may not be suitable for clocking data converters. The

jitter is higher for long full scales because the delay block uses a

ramp and trip points to create the variable delay. A slower ramp

time produces more time jitter.

Synchronizing the Outputs—SYNC Function

The AD9516 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and subsequently releasing these

outputs to continue clocking at the same instant with the preset

conditions applied. This allows for the alignment of the edges of

two or more outputs or for the spacing of edges according to the

coarse phase offset settings for two or more outputs.

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