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AD9516-2/PCBZ Fiches technique(PDF) 67 Page - Analog Devices

No de pièce AD9516-2/PCBZ
Description  14-Output Clock Generator with Integrated 2.2 GHz VCO
PDF  84 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9516-2/PCBZ Fiches technique(HTML) 67 Page - Analog Devices

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AD9516-2
Rev. 0 | Page 67 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
1D
<3>
LD Pin
Comparator
Enable
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When in the internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to
determine if the PLL was previously in a locked state (see Figure 51). Otherwise, this can be used with
the REFMON and STATUS pins to monitor the voltage on this pin.
<3> = 0; disable LD pin comparator; internal/automatic holdover controller treats this pin as true (high).
<3> = 1; enable LD pin comparator.
1D
<2>
Holdover
Along with <0> enables the holdover function.
Enable
<2> = 0; holdover disabled.
<2> = 1; holdover enabled.
1D
<1>
External
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
Holdover
<1> = 0; automatic holdover mode—holdover controlled by automatic holdover circuit.
Control
<1> = 1; external holdover mode—holdover controlled by SYNC pin.
1D
<0>
Holdover
Along with <2> enables the holdover function.
Enable
<0> = 0; holdover disabled.
<0> = 1; holdover enabled.
1F
<6>
VCO Cal
Readback register: status of the VCO calibration.
Finished
<6> = 0; VCO calibration not finished.
<6> = 1; VCO calibration finished.
1F
<5>
Holdover
Active
Readback register: indicates if the part is in the holdover state (see Figure 51). This is not the same as
holdover enabled.
<5> = 0; not in holdover.
<5> = 1; holdover state active.
1F
<4>
REF2
Readback register: indicates which PLL reference is selected as the input to the PLL.
Selected
<4> = 0; REF1 selected (or differential reference if in differential mode).
<4> = 1; REF2 selected.
1F
<3>
VCO
Frequency >
Readback register: indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and
VCO Frequency Status Monitor).
Threshold
<3> = 0; VCO frequency is less than the threshold.
<3> = 1; VCO frequency is greater than the threshold.
1F
<2>
REF2
Frequency >
Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x1A<6>.
Threshold
<2> = 0; REF2 frequency is less than threshold frequency.
<2> = 1; REF2 frequency is greater than threshold frequency.
1F
<1>
REF1
Frequency >
Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x1A<6>.
Threshold
<1> = 0; REF1 frequency is less than threshold frequency.
<1> = 1; REF1 frequency is greater than threshold frequency.
1F
<0>
Digital Lock
Readback register: digital lock detect.
Detect
<0> = 0; PLL is not locked.
<0> = 1; PLL is locked.



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