AD9516-2SLASHPCBZ datasheet(63/84 Pages) AD

63 / 84 page

AD9516-2

Rev. 0 | Page 63 of 84

Reg.

Addr

(Hex) Bit(s) Name

Description

<7>

<6> <5> <4>

<3>

<2>

Level or

Dynamic

Signal

Signal at STATUS Pin

LVL

LD pin comparator output (active high).

LVL

VS (PLL supply).

DYN

REF1 clock (differential reference when in differential mode).

DYN

REF2 clock (not available in differential mode).

DYN

Selected reference to PLL (differential reference when in

differential mode).

DYN

Unselected reference to PLL (not available when in

differential mode).

LVL

Status of selected reference (status of differential reference);

active low.

LVL

Status of unselected reference (not available in differential

mode); active low.

LVL

Status of REF1 frequency (active low).

LVL

Status of REF2 frequency (active low).

LVL

(Status of REF1 frequency) AND (Status of REF2 frequency).

LVL

(DLD) AND (Status of selected reference) AND (Status of VCO).

LVL

Status of VCO Frequency (active low).

LVL

Selected reference (low = REF2, high = REF1).

LVL

Digital lock detect (DLD) (active low).

LVL

Holdover active (active low).

LVL

LD pin comparator output (active low).

<1:0> Antibacklash <1>

<0>

Antibacklash Pulse Width (ns)

Pulse Width

2.9

1.3

6.0

2.9

<6:5> Lock Detect

Counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates

a locked condition.

<6>

<5>

PFD Cycles to Determine Lock

255

<4>

Digital Lock

Detect

If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the

digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

Window

<4> = 0; high range.

<4> = 1; low range.

<3>

Disable

Digital lock detect operation.

Digital

<3> = 0; normal lock detect operation.

Lock Detect

<3> = 1; disable lock detect.

<2:1> VCO Cal

VCO Calibration Divider. Divider used to generate the VCO calibration clock from the PLL reference clock.

Divider

<2>

<1>

VCO Calibration Clock Divider

16 (default)

<0>

VCO Cal Now Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The sequence

to initiate a calibration is: program to a 0, followed by an update bit (Register 0x232<0>); then programmed to

1, followed by another update bit (Register 0x232<0>). This sequence gives complete control over when the

VCO calibration occurs relative to the programming of other registers that can impact the calibration.

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