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AS7030B

Electrical Characteristics

Datasheet

• PUBLIC

DS000716

• v1-00 • 2020-Jun-10

128

│ 15

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tLOW

LOW period

of SCL clock

1.3

µs

tHIGH

HIGH period

of SCL clock

0.6

µs

tSU:STA

Setup time for

a repeated

START

condition

0.6

µs

tHD:DAT

Data hold

time(5)

0.9

µs

tSU:DAT

Data setup

time(6)

100

Rise time of

both SDA and

SCL signals

300

Fall time of

Both SDA

and SCL

signals

300

tSU:STO

Setup time for

STOP

condition

0.6

µs

Capacitive

load for each

bus line

— total capacitance

of one bus line in pF

500

CI/O

I/O pin

capacitance

(SDA, SCL)

(1)

GPIO0-3 configured to draw minimum current (software dependent).

(2)

AS7030B I2C interface active also in power down mode

(3)

Specified only typical value for DNL to reduce production test time.

(4)

After this period, the first clock pulse is generated.

(5)

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

(6)

Fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250 ns must then be met.

This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does

stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 =

1250 ns before the SCL line is released.

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