AS7030B datasheet(69/129 Pages) AMSCO

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AS7030B

Functional Description

Datasheet

• PUBLIC

DS000716

• v1-00 • 2020-Jun-10

128

│ 68

OFE1_CFGA (Address 0x54)

Figure 80:

OFE1_CFGA Register

Addr: 0x54

OFE1_CFGA

Bit

Bit Name

Default

Access

Bit Description

ofe1_sd_pol_init

The low level driver shall ensure that this register

is 0 if one of the seq_sdm pulses is first, and is 1

if the seq_sdp is first within a sequence.

ofe1_sd_en

0: Power down of the Synchronous demodulator

1: Enable Synchronous demodulator

ofe1_hp_en

0: Power down of the high pass filter

1: Enable high pass filter

ofe1_gain_en

0: Power down of the Gain stage

1: Enable Gain stage

ofe1_sd_byp

0: Synchronous demodulator is used

1: Synchronous demodulator is bypassed

ofe1_hp_byp

0: HP filter is used

1: HP filter is bypassed

ofe1_gain_byp

0: Gain stage is used

1: Gain stage is bypassed

ofe1_sd_hld

SD hold

0: Output of synchronous demodulator is forced

to SIGREF if not set to +1 or -1

1: Output of synchronous demodulator is

tristated if not set to +1 or -1

OFE1_CFGB (Address 0x55)

Figure 81:

OFE1_CFGB Register

Addr: 0x55

OFE1_CFGB

Bit

Bit Name

Default

Access

Bit Description

7:5

ofe1_gain_g

Gain for synchronous demodulator 1.

Settings

Gain

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