ADE9000ACPZ datasheet(11/73 Pages) AD

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ADE9000

Data Sheet

Rev. A | Page 10 of 72

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PULL_HIGH

DGND

DVDDOUT

PM0

PM1

RESET

IAP

IAN

IBP

IBN

23 VCN

24 VCP

25 AVDDOUT

26 AGND

27 VDD

28 GND

29 CLKIN

30 CLKOUT

22 VBP

21 VBN

ADE9000

TOP VIEW

(Not to Scale)

NOTES

1. IT IS RECOMMENDED TO TIE THE

NC1 AND NC2 PINS TO GROUND.

2. EXPOSED PAD. CREATE A SIMILAR PAD ON THE

PRINTED CIRCUIT BOARD (PCB) UNDER THE

EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE

PAD ON THE PCB TO CONFER MECHANICAL STRENGTH

TO THE PACKAGE AND CONNECT ALL GROUNDS

(GND, AGND, DGND, AND REFGND) TOGETHER AT

THIS POINT.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

PULL_HIGH

Pull High. Tie this pin to VDD.

DGND

Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9000. Because the

digital return currents in the ADE9000 are small, it is acceptable to connect this pin to the analog ground

plane of the whole system. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

DVDDOUT

1.8 V Output of the Digital Low Dropout Regulator (LDO). Decouple this pin with a 0.1 µF ceramic

capacitor in parallel with a 4.7 µF ceramic capacitor.

PM0

Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, ground

PM0 and PM1.

PM1

Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, ground PM0

and PM1.

RESET

Reset Input, Active Low. This pin must stay low for at least 1 µs to trigger a hardware reset.

7, 8

IAP, IAN

Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs

with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

9, 10

IBP, IBN

Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs

with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

11, 12

ICP, ICN

Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs

with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

13, 14

INP, INN

Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage inputs

with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

REFGND

Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND)

together at one point.

REF

Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference

has a nominal value of 1.25 V. An external reference source of 1.2 V to 1.25 V can also be connected at this

pin. In either case, decouple REF to REFGND with 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic

capacitor. After reset, the on-chip reference is enabled. To use the internal voltage reference with external

circuits, a buffer is required.

NC1

No Connection. It is recommended to tie this pin to ground.

NC2

No Connection. It is recommended to tie this pin to ground.

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