ADE9000ACPZ datasheet(69/73 Pages) AD

69 / 73 page

ADE9000

Data Sheet

Rev. A | Page 68 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

WF_CAP_SEL

This bit selects whether the waveform buffer is

filled with resampled data or fixed data rate

data, selected in the WF_CAP_SEL bits.

0x0

R/W

0 Resampled data.

1 Fixed data rate data.

WF_CAP_EN

When this bit is set, a waveform capture is started.

0x0

R/W

0 The waveform capture is disabled. The waveform

buffer contents are maintained.

1 The waveform capture is started, according to

the type of capture in WF_CAP_SEL and the

WF_SRC bits when this bit goes from a 0 to a 1.

[3:0]

BURST_CHAN

Selects which data to read out of the waveform

buffer through SPI.

0x0

R/W

0000 All channels.

0001 IA and VA.

0010 IB and VB.

0011 IC and VC.

1000 IA.

1001 VA.

1010 IB.

1011 VB.

1100 IC.

1101 VC.

1110 IN if WF_IN_EN = 1 in the WFB_CFG register.

1111 Single address read (SPI burst read mode is

disabled).

0x4A2 WFB_TRG_CFG [15:11] RESERVED

Reserved.

0x0

TRIG_FORCE

Set this bit to trigger an event to stop the

waveform buffer filling.

0x0

R/W

ZXCOMB

Zero crossing on combined signal from VA, VB,

and VC.

0x0

R/W

ZXVC

Phase C voltage zero crossing.

0x0

R/W

ZXVB

Phase B voltage zero crossing.

0x0

R/W

ZXVA

Phase A voltage zero crossing.

0x0

R/W

ZXIC

Phase C current zero crossing.

0x0

R/W

ZXIB

Phase B current zero crossing.

0x0

R/W

ZXIA

Phase A current zero crossing.

0x0

R/W

Over current event in any phase.

0x0

R/W

SWELL

Swell event in any phase.

0x0

R/W

DIP

Dip event in any phase.

0x0

R/W

0x4A3 WFB_TRG_STAT [15:12] WFB_LAST_PAGE

These bits indicate which page of the waveform

buffer was filled last, when filling with fixed rate

data samples.

0x0

R/W

RESERVED

Reserved.

0x0

[10:0]

WFB_TRIG_ADDR

These bits hold the address of the last sample

put into the waveform buffer after a trigger

event occurred, which is within a sample or two

of when the actual trigger event occurred.

0x0

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