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ADE9000ACPZ Fiches technique(PDF) 70 Page - Analog Devices |
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ADE9000ACPZ Fiches technique(HTML) 70 Page - Analog Devices |
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70 / 73 page ![]() Data Sheet ADE9000 Rev. A | Page 69 of 72 Addr. Name Bits Bit Name Settings Description Reset Access 0x4AF CONFIG2 [15:13] RESERVED Reserved. 0x0 R 12 UPERIOD_SEL Set this bit to use a user configured line period, in USER_PERIOD, for the VRMS½, 10 cycle rms/ 12 cycle rms and resampling calculation. If this bit is clear, the phase voltage line period selected by the LP_SEL[1:0] bits in the ZX_LP_SEL register is used. 0x0 R/W [11:9] HPF_CRN High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero. 0x6 R/W 000 77.39 Hz. 001 39.275 Hz. 010 19.79 Hz. 011 9.935 Hz. 100 4.98 Hz. 101 2.495 Hz. 110 1.25 Hz. 111 0.625 Hz. [8:0] RESERVED Reserved. 0x0 R 0x4B0 EP_CFG [15:13] NOLOAD_TMR This register configures how many 8 kSPS samples to evaluate the no load condition over. 0x0 R/W 000 64 samples. 001 128 samples. 010 256 samples. 011 512 samples. 100 1024 samples. 101 2048 samples. 110 4096 samples. 111 Disable no load threshold. [12:8] RESERVED Reserved. 0x0 R 7 PWR_SIGN_SEL[1] Selects whether the REVRPx bit follows the sign of the total or fundamental reactive power. 0x0 R/W 0 Total reactive power. 1 Fundamental reactive power. 6 PWR_SIGN_SEL[0] Selects whether the REVAPx bit follows the sign of the total or fundamental active power. 0x0 R/W 0 Total active power. 1 Fundamental active power. 5 RD_RST_EN Set this bit to enable the energy register read with reset feature. If this bit is set, when one of the xWATTHR, xVAHR, xVARH, xFWATTHR, xFVAHR, and xFVARHR register is read, it is reset and begins accumulating energy from zero. 0x0 R/W 4 EGY_LD_ACCUM If this bit is equal to zero, the internal energy register is added to the user accessible energy register. If the bit is set, the internal energy register overwrites the user accessible energy register when the EGYRDY event occurs. 0x0 R/W [3:2] RESERVED Reserved. 0x0 R |
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