ADE9000ACPZ datasheet(55/73 Pages) AD

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ADE9000

Data Sheet

Rev. A | Page 54 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

REVPSUM4

This bit is set to indicate if the CF4 polarity

changed sign. For example, if the last CF4 pulse

was positive reactive energy and the next CF4

pulse is negative reactive energy, the REVPSUM4

bit is set. This bit is updated when a CF4 pulse is

output, when the CF4 pin goes from high to low.

0x0

R/W1

REVPSUM3

This bit is set to indicate if the CF3 polarity

changed sign. See REVPSUM4.

0x0

R/W1

REVPSUM2

This bit is set to indicate if the CF2 polarity

changed sign. See REVPSUM4.

0x0

R/W1

REVPSUM1

This bit is set to indicate if the CF1 polarity

changed sign. See REVPSUM4.

0x0

R/W1

REVRPC

This bit indicates if the Phase C total or

fundamental reactive power has changed sign.

The PWR_SIGN_SEL bit in the EP_CFG register

selects whether total or fundamental reactive

power is monitored. This bit is updated when the

power values in the xVAR_ACC and xFVAR_ACC

registers update, after PWR_TIME 8 kSPS samples.

0x0

R/W1

REVRPB

This bit indicates if the Phase B total or

fundamental reactive power has changed sign.

See REVRPC.

0x0

R/W1

REVRPA

This bit indicates if the Phase A total or

fundamental reactive power has changed sign.

See REVRPC.

0x0

R/W1

REVAPC

This bit indicates if the Phase C total or

fundamental active power has changed sign.

The PWR_SIGN_SEL bit in the EP_CFG register

selects whether total or fundamental active power

is monitored. This bit is updated when the power

values in the xWATT_ACC and xFWATT_ACC

registers update, after PWR_TIME 8 kSPS samples.

0x0

R/W1

REVAPB

This bit indicates if the Phase B total or

fundamental active power has changed sign.

See REVAPC.

0x0

R/W1

REVAPA

This bit indicates if the Phase A total or

fundamental active power has changed sign.

See REVAPC.

0x0

R/W1

EGYRDY

This bit is set when the power values in the

xWATTHR xVAHR, xVARHR, xFVARHR, xFWATTHR,

xFVAHR registers update, after EGY_TIME 8 kSPS

samples or line cycles, depending on the

EGY_TMR_MODE bit in the EP_CFG register.

0x0

R/W1

0x403 STATUS1

ERROR3

This bit indicates an error and generates a non-

maskable interrupt. Issue a software or hardware

reset to clear this error.

0x0

R/W1

ERROR2

This bit indicates that an error was detected and

corrected. No action is required.

0x0

R/W1

ERROR1

This bit indicates an error and generates a non-

maskable interrupt. Issue a software or hardware

reset to clear this error.

0x0

ERROR0

This bit indicates an error and generates a non-

maskable interrupt. Issue a software or hardware

reset to clear this error.

0x0

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