ADE9000ACPZ datasheet(54/73 Pages) AD

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Data Sheet

ADE9000

Rev. A | Page 53 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x401 VPEAK

[31:27] RESERVED

Reserved.

0x0

[26:24] VPPHASE

These bits indicate which phase(s) generate the

VPEAKVAL value. Note that the PEAKSEL,

Bits[4:2] in the CONFIG3 register determine which

voltage channels to monitor the peak value on.

When VPPHASE, Bit 0 is 1, the Phase A voltage

generated the VPEAKVAL, Bits[23:0] value.

Similarly, VPPHASE, Bit 1 indicates Phase B and

VPPHASE, Bit 2 indicates that the Phase C

voltage generated the peak value.

0x0

[23:0]

VPEAKVAL

The VPEAK register stores the absolute value of

the peak voltage. VPEAK is equal to xV_PCF/25.

0x0

0x402 STATUS0

[31:26] RESERVED

Reserved.

0x0

TEMP_RDY

This bit goes high to indicate when a new

temperature measurement is available.

0x0

R/W1

MISMTCH

This bit is set to indicate a change in the

relationship between ISUMRMS and ISUMLVL.

0x0

R/W1

COH_WFB_FULL

This bit is set when the waveform buffer is full

with resampled data, which is selected when

WF_CAP_SEL = 0 in the WFB_CFG register.

0x0

R/W1

WFB_TRIG

This bit is set when one of the events configured

in WFB_TRIG_CFG occurs.

0x0

R/W1

THD_PF_RDY

This bit goes high to indicate when the THD and

power factor measurements update, every 1.024

sec.

0x0

R/W1

RMS1012RDY

This bit is set when the 10 cycle rms/12 cycle rms

values update.

0x0

R/W1

RMSONERDY

This bit is set when the fast rms½ rms values

update.

0x0

R/W1

PWRRDY

This bit is set when the power values in the

xWATT_ACC, xVA_ACC, xVAR_ACC, xFWATT_ACC,

xFVA_ACC, and xFVAR_ACC registers update,

after PWR_TIME 8 kSPS samples.

0x0

R/W1

PAGE_FULL

This bit is set when a page enabled in the

WFB_PG_IRQEN register is filled with fixed data

rate samples, when WF_CAP_SEL bit in the

WFB_CFG register is equal to zero.

0x0

R/W1

WFB_TRIG_IRQ

This bit is set when the waveform buffer stops

filling after an event configured in WFB_TRIG_CFG

occurs. This happens with fixed data rate samples

only, when WF_CAP_SEL bit in the WFB_CFG

0x0

R/W1

DREADY

This bit is set when new waveform samples are

ready. The update rate depends on the data

selected in the WF_SRC bits in the WFB_CFG

0x0

R/W1

CF4

This bit is set when a CF4 pulse is issued, when

the CF4 pin goes from a high to low state.

0x0

R/W1

CF3

This bit is set when a CF3 pulse is issued, when

the CF3 pin goes from a high to low state.

0x0

R/W1

CF2

This bit is set when a CF2 pulse is issued, when

the CF2 pin goes from a high to low state.

0x0

R/W1

CF1

This bit is set when a CF1 pulse is issued, when

the CF1 pin goes from a high to low state.

0x0

R/W1

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