ADE9000ACPZ datasheet(68/73 Pages) AD

68 / 73 page

Data Sheet

ADE9000

Rev. A | Page 67 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x49D PHSIGN

[15:10] RESERVED

Reserved.

0x0

SUM4SIGN

Sign of the sum of the powers included in the

CF4 datapath. The CF4 energy is positive if this

bit is clear and negative if this bit is set.

0x0

SUM3SIGN

Sign of the sum of the powers included in the

CF3 datapath. The CF3 energy is positive if this

bit is clear and negative if this bit is set.

0x0

SUM2SIGN

Sign of the sum of the powers included in the

CF2 datapath. The CF2 energy is positive if this

bit is clear and negative if this bit is set.

0x0

SUM1SIGN

Sign of the sum of the powers included in the

CF1 datapath. The CF1 energy is positive if this

bit is clear and negative if this bit is set.

0x0

CVARSIGN

Phase C reactive power sign bit. The PWR_SIGN_

SEL bit in the EP_CFG selects whether this feature

monitors total or fundamental reactive power.

0x0

CWSIGN

Phase C active power sign bit. The PWR_SIGN_SEL

bit in the EP_CFG selects whether this feature

monitors total or fundamental active power.

0x0

BVARSIGN

Phase B reactive power sign bit. The PWR_SIGN_

SEL bit in the EP_CFG selects whether this feature

monitors total or fundamental reactive power.

0x0

BWSIGN

Phase B active power sign bit. The PWR_SIGN_SEL

bit in the EP_CFG selects whether this feature

monitors total or fundamental active power.

0x0

AVARSIGN

Phase A reactive power sign bit. The PWR_SIGN_

SEL bit in the EP_CFG selects whether this feature

monitors total or fundamental reactive power.

0x0

AWSIGN

Phase A active power sign bit. The PWR_SIGN_SEL

bit in the EP_CFG selects whether this feature

monitors total or fundamental active power.

0x0

0x4A0 WFB_CFG

[15:13] RESERVED

Reserved.

0x0

WF_IN_EN

This setting determines whether the IN waveform

samples are read out of the waveform buffer

through the SPI.

0x0

R/W

0 IN waveform samples are not read out of

waveform buffer through the SPI.

1 IN waveform samples are read out of waveform

buffer through the SPI.

[11:10] RESERVED

Reserved.

0x0

[9:8]

WF_SRC

Waveform buffer source and DREADY (data

ready update rate) selection.

0x0

R/W

00 Sinc4 output at 32 kSPS.

01 Reserved.

10 Sinc4 + IIR LPF output at 8 kSPS.

11 Current and voltage channel waveform samples,

processed by the DSP (xI_PCF, xV_PCF) at 8 kSPS.

[7:6]

WF_MODE

Fixed data rate waveforms filling and trigger

based modes.

0x0

R/W

00 Stop when waveform buffer is full.

01 Continuous fill—stop only on enabled trigger

events.

10 Continuous filling—center capture around

enabled trigger events.

11 Continuous fill—save event address of enabled

trigger events.

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