ADE9000ACPZ datasheet(60/73 Pages) AD

60 / 73 page

Data Sheet

ADE9000

Rev. A | Page 59 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x406 MASK1

ERROR3

Set this bit to enable an interrupt if ERROR3 occurs.

Issue a software reset or hardware reset to clear

this error.

0x0

R/W

ERROR2

Set this bit to enable an interrupt if ERROR2 occurs. 0x0

R/W

ERROR1

This interrupt is not maskable. Issue a software

reset or hardware reset to clear this error.

0x0

R/W

ERROR0

This interrupt is not maskable. Issue a software

reset or hardware reset to clear this error.

0x0

R/W

CRC_DONE

Set this bit to enable an interrupt when the

configuration register CRC calculation is complete,

after initiated by writing the FORCE_CRC_UPDATE

bit in the CRC_FORCE register.

0x0

R/W

CRC_CHG

Set this bit to enable an interrupt if any of the

registers monitored by the configuration register

CRC change value. The CRC_RSLT register holds

the new configuration register CRC value.

0x0

R/W

DIPC

Set this bit to enable an interrupt when the

Phase C voltage enters a dip condition

0x0

R/W

DIPB

Set this bit to enable an interrupt when the

Phase B voltage enters a dip condition.

0x0

R/W

DIPA

Set this bit to enable an interrupt when the

Phase A voltage enters a dip condition.

0x0

R/W

SWELLC

Set this bit to enable an interrupt when the

Phase C voltage enters a swell condition.

0x0

R/W

SWELLB

Set this bit to enable an interrupt when the

Phase B voltage enters a swell condition.

0x0

R/W

SWELLA

Set this bit to enable an interrupt when the

Phase A voltage enters a swell condition.

0x0

R/W

RESERVED

Reserved.

0x0

SEQERR

Set this bit to enable an interrupt when on a

phase sequence error on the phase voltage zero

crossings.

0x0

R/W

Set this bit to enable an interrupt when one of

the currents enabled in the OC_EN bits in the

CONFIG3 register enters an overcurrent condition.

0x0

R/W

RESERVED

Reserved.

0x0

ZXIC