ADE9000ACPZ datasheet(62/73 Pages) AD

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Data Sheet

ADE9000

Rev. A | Page 61 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

REVPSUM3

Set this bit to enable the EVENT pin to go low to

indicate if the last CF3 pulse was from negative

energy. This bit is updated when a CF3 pulse is

output, when the CF3 pin goes from high to low.

0x0

R/W

REVPSUM2

Set this bit to enable the EVENT pin to go low to

indicate if the last CF2 pulse was from negative

energy. This bit is updated when a CF2 pulse is

output, when the CF2 pin goes from high to low.

0x0

R/W

REVPSUM1

Set this bit to enable the EVENT pin to go low to

indicate if the last CF1 pulse was from negative

energy. This bit is updated when a CF1 pulse is

output, when the CF1 pin goes from high to low.

0x0

R/W

SWELLCEN

Set this bit to enable the EVENT pin to go low to

indicate that the Phase C voltage is in a swell

condition.

0x0

R/W

SWELLBEN

Set this bit to enable the EVENT pin to go low to

indicate that the Phase B voltage is in a swell

condition.

0x0

R/W

SWELLAEN

Set this bit to enable the EVENT pin to go low to

indicate that the Phase A voltage is in a swell

condition.

0x0

R/W

DIPCEN

Set this bit to enable the EVENT pin to go low to

indicate that the Phase C voltage is in a dip

condition.

0x0

R/W

DIPBEN

Set this bit to enable the EVENT pin to go low to

indicate that the Phase B voltage is in a dip

condition.

0x0

R/W

DIPAEN

Set this bit to enable the EVENT pin to go low to

indicate that the Phase A voltage is in a dip

condition.

0x0

R/W

0x409 OILVL

[31:24] RESERVED

Reserved.

0x0

[23:0]

OILVL_VAL

Over current detection threshold level.

0xFFFFFF R/W

0x40A OIA

[31:24] RESERVED

Reserved.

0x0

[23:0]

OI_VAL

Phase A overcurrent rms½ value. If a phase is

enabled, with the OC_ENA bit set in the CONFIG3

threshold, this value is updated.

0x0

0x40B OIB

[31:24] RESERVED

Reserved.

0x0

[23:0]

OIB_VAL

Phase B overcurrent rms½ value. If a phase is

enabled, with the OC_ENB bit set in the CONFIG3

threshold, this value is updated.

0x0

0x40C OIC

[31:24] RESERVED

Reserved.

0x0

[23:0]

OIC_VAL

Phase C overcurrent rms½ value. If a phase is

enabled, with the OC_ENC bit set in the CONFIG3

threshold, this value is updated.

0x0

0x40D OIN

[31:24] RESERVED

Reserved.

0x0

[23:0]

OIN_VAL

Neutral current overcurrent rms½ value. If

enabled, with the OC_ENN bit set in the CONFIG3

threshold, this value is updated.

0x0

0x40F VLEVEL

[31:24] RESERVED

Reserved.

0x0

[23:0]

VLEVEL_VAL

the fundamental active, reactive, and apparent

powers, as well as the fundamental IRMS and VRMS

values.

0x45D45 R/W

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