L99MM70XP datasheet(51/68 Pages) STMICROELECTRONICS

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L99MM70XP

SPI control and status registers

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SPI control and status registers

9.1

Functional description of the SPI

For a general description of the SPI please refer to chapter Serial peripheral interface (ST

SPI standard).

9.1.1

SPI communication flow

At the beginning of each communication the master can read the contents of the <SPI-

frame-ID> register (ROM address 3Eh) of the slave device. This 8 bit register indicates the

SPI frame length (24 bit) and the availability of additional features.

Each communication frame consists of a command byte which is followed by 2 data bytes.

The data returned on DO within the same frame always starts with the <Global Status

Byte>. It provides general status information about the device. It is followed by 2 data bytes

(i.e. “in-frame-response”).

For write cycles the <Global Status Byte> is followed by the previous content of the

addressed register.

9.1.2

Command byte

OCx: operation code

Ax: address

Dx: data bit

Each communication frame starts with a command byte. It consists of an operating code

which specifies the type of operation (<Read>, <Write>, <Read and Clear>, <Read Device

Information>) and a 6 bit address. If less than 6 bits are required, the remaining bits are

unused but are reserved.

9.1.3

Operation code definition

Table 27.

Command byte

Data byte 1

Data byte 2

Bit

76543

210

Name

OC1

OC0

D15 D14 D13 D12 D11 D10

Table 28.

Operation code definition

OC1

OC0

Meaning

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