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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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L99MM70XP Fiches technique(PDF) 18 Page - STMicroelectronics |
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L99MM70XP Fiches technique(HTML) 18 Page - STMicroelectronics |
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18 / 68 page  Description L99MM70XP 18/68 Doc ID 022637 Rev 2 Figure 5. Watchdog state diagram 3.7 Passive mode L99MM70XP enters passive mode in case of: ● Watchdog failure ● VCC under voltage (NRES) ● Thermal shutdown TSD2 ● SPI data in stuck at 0 or 1 In passive mode all control registers (except the reset level bit RSTLVL) and the configuration register are set to default so that all outputs are switched off. The PASSIVE bit inside the global status byte is set to “1”. The first valid SPI frame after entering the passive mode resets the PASSIVE bit to “0” and leaves passive. 3.8 Reset output (NRES) If VCC is turned on and the voltage exceeds the VCC reset threshold, the reset output NRES is pulled up by internal pull up resistor to VCC voltage after a 2 ms reset delay time. This is necessary for a defined start of the microcontroller when the application is switched on. A low active reset pulse (2 ms) is generated in case of: ● VCC drops below Vrth (configurable by SPI) for more than 8 µs (VCC under voltage) ● Watchdog failure |
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