L99MM70XP datasheet(21/68 Pages) STMICROELECTRONICS

21 / 68 page

L99MM70XP

Description

Doc ID 022637 Rev 2

21/68

3.11

Controller for electrochromic glass

The voltage of an electrochromic element connected at pin ECV can be controlled to a

target value, which is set by the bits EC<5:0> (Control register 2, bits 6 down to 1). Setting

bit ECON (control register 2, bit 0) enables this function. An on-chip differential amplifier and

an external MOS source follower, with its gate connected to pin ECDR, and which drives the

electrochrome mirror voltage at pin ECV, form the control loop. The drain of the external

MOS transistor is supplied by OUT7. A diode from pin ECV (anode) to pin ECDR (cathode)

has been placed on the chip to protect the external MOS source follower. A capacitor of at

least 5 nF has to be added to pin ECDR for loop-stability. The target voltage is binary coded

with a full-scale range of 1.5 V. If bit ECVL (control register 3, bit 5) is set to '1', the maximum

controller output voltage is clamped to 1.2 V without changing the resolution of bits

EC<5:0>. When programming the ECVLS driver to on-state, the voltage at pin ECV is pulled

to ground by a 1.6 Ohm low-side switch until the voltage at pin ECV is less than dVECVhi

higher than the target voltage (fast discharge).

The status of the voltage control loop is reported via SPI. Bit ECVO (status register 3, bit 4)

is set, if the voltage at pin ECV is higher, whereas bit ECVNR (status register 3, bit 5) is set,

if the voltage at pin ECV is lower than the target value. Both status bits are valid, if the

voltage is stable for at least the ECVO/ECVNR filter time and are not latched.

Since OUT7 is the output of a high-side driver, it contains the same diagnose functions as

the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched

off). In electrochrome mode, OUT10 cannot be controlled by PWM mode. For EMS reasons

the loop capacitor at pin ECDR as well as the capacitor between ECV and GND have to be

placed to the respective pins as close as possible (see Figure 13 for details).

If the electrochrome element is connected between the pins ECV and ECFD instead

between ECV and ground, a negative voltage can be applied to the device by pulling ECFD

to a higher value than ECV, which is connected to ground by a 1.6 Ohm low-side switch. In

this mode the voltage at pin ECFD is controlled to the target value defined by the register

EC<5:0>. This is done using an on-chip source-follower transistor (see Figure 14 for

details). The negative discharge is enabled by setting bit ECND (control register 2, bit 7) to

‘1’.

During normal (positive) voltage control the low-side driver at pin ECFD must be switched

on to connect the electrochrome element to ground.

Pin ECDR is pulled resistively (RECDRDIS) to ground while not in electrochrome mode.

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