L99MM70XP datasheet(63/68 Pages) STMICROELECTRONICS

63 / 68 page

L99MM70XP

SPI control and status registers

Doc ID 022637 Rev 2

63/68

All bits except the WDTIM1, WDTIM0, ECVNR and ECVO bits can be reset by a read and

clear operation on SR4.

Table 48.

Status register 4

Status register 4 (14h)

Bit

210

Reset state

0000

Name

fail

Forced

SleepWD

Forced

SleepTSD

Dev

State

Dev

State

VCC

Restart

VCC

Restart

VCC

Restart

NOT

RDY

SPI

Wake

LIN

Wake

INH

Wake

Table 49.

Status register 4, bits

Bit name

Comment

WDFAIL3

Nr of watchdog fails

These bits are not clearable, are

cleared with a proper watchdog trigger

or if the chip is sent to VBAT-standby by

the watchdog.

WDFAIL2

WDFAIL1

WDFAIL0

Forced sleep

This bit is set if the chip has been set to VBAT-standby mode

by the watchdog

These bits are latched until a “read and

clear” access on SR4.

Forced sleep

TSD

This bit is set if the chip has been set to VBAT-standby mode

by a thermal shutdown

DEVSTATE1

Signal device state:

The device state is updated with any state transition and

with a read and clear command on status register 4.

Therefore, the first read operation after entering active

mode or flash mode reads the last device state. Read

operations after a read and clear operation reads the

current device state. After power-on reset, the device

state is VBAT-standby.

These bits are latched until a “read and

clear” access on SR 4.

DEVSTATE0

VCCRestart2

Nr of TSD restart trials

These bits are latched until a “read and

clear access” on SR 4.

VCCRestart1

VCCRestart0

NOTRDY

Not ready: This bit is set for 200µs after switching from

standby to active mode. It is cleared automatically. While

the bit is set, the output drivers are disabled.

This bit is not clearable, it is cleared

automatically.

DEV

STATE1

DEV

STATE2

State

Active

VCC-standby

VBAT standby or POR

Flash

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