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L99MM70XP Fiches technique(PDF) 47 Page - STMicroelectronics

No de pièce L99MM70XP
Description  INH input for external CAN transceiver
PDF  68 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99MM70XP Fiches technique(HTML) 47 Page - STMicroelectronics

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L99MM70XP
Electrical characteristics
Doc ID 022637 Rev 2
47/68
8.11.2
AC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V
 V
S  18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
8.11.3
Dynamic characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V
 V
S  18 V; all outputs open; Tamb = -40 °C...125 °C, unless
otherwise specified.
For definition of the parameters please see Figure 16 and Figure 17.
Table 24.
AC characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
COUT
(1)
1.
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Output capacitance (DO)
—
—
10
pF
CIN
(1)
Input capacitance (DI, CSN,
CLK, PWM1, PWM2, PWM3)
——
10
pF
Table 25.
Dynamic characteristics
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
tCSNQVL
DO enable from 3-state to
low-level
CDO = 100 pF, IDO = 1 mA, pull
up load to VCC, VS = 13.5 V
100
250
ns
tCSNQVH
DO enable from 3-state to
high-level
CDO = 100 pF, IDO =-1 mA, pull
down load to GND, VS = 13.5 V
100
250
ns
tCSNQTL
DO disable from low-level to
3-state
CDO = 100 pF, IDO = 4 mA, pull
up load to VCC, VS = 13.5 V
380
450
ns
tCSNQTH
DO disable from high-level to
3-state
CDO = 100 pF, IDO = -4 mA, pull
down load to GND, VS = 13.5 V
380
450
ns
tCLKQV CLK falling until DO valid
VDO <0.3 VCC or VDO >0.7 VCC
CDO =5pF, VS =13.5V
ns
VDO <0.3 VCC or VDO >0.7 VCC
CDO = 100 pF, VS =13.5V
50
250
ns
tSCSN
CSN setup time, CSN low
before rising edge of CLK
VS = 13.5 V
400
ns
tSDI
DI setup time, DI stable before
rising edge of CLK
VS = 13.5 V
200
ns
tHDI
DI hold time, DI stable after
rising edge of CLK
VS = 13.5 V
200
ns
tHCLK
minimum CLK high time
VS = 13.5 V
115
ns
tLCLK
minimum CLK low time
VS = 13.5 V
115
ns
tHCSN minimum CSN high time
VS = 13.5 V
4µs
tSCLK
CLK setup time before CSN
rising
VS = 13.5 V
400
ns



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