L99MM70XP datasheet(54/68 Pages) STMICROELECTRONICS

54 / 68 page

SPI control and status registers

L99MM70XP

54/68

Doc ID 022637 Rev 2

9.1.6

Control registers

Table 32.

Control registers 1

Control register 1 (01h)

Bit

13121110

Reset state

000000

Name

OUT5

OUT4

OUT3

OUT2

OUT1

NINT

RST

LEV

ICMP

Stby

Sel

Stby

Trig

Table 33.

Control registers 1, bits

Bit name

Comment

OUT5HS

If a bit is set, the selected output driver is switched on. If the corresponding PWM enable bit is set

also, the driver is activated only if the associated PWM input signal is high.

The outputs of OUT1 – OUT5 are half bridges. If the bits of the HS and LS drivers of the same half

bridge are set, both drivers are deactivated and the output is set to high impedance.

OUT5LS

OUT4HS

OUT4LS

OUT3HS

OUT3LS

OUT2HS

OUT2LS

OUT1HS

OUT1LS

NINTEN

Enable NINT output

0: RXD output has only RXD functionality

1: RXD output can work also as NINT output

RSTLEV

Select VCC reset level

0: 4.7 V

1: 3.5 V

ICMP

Monitor the ICC current consumption during VCC-standby mode

0: watchdog disabled only if ICC < ICMP

1: watchdog disabled

STBYSEL

Standby select

0: VBAT-standby

1: VCC-standby

This bit is a one-shot bit, it is read always 0

GOSTBY

1: execute standby mode

This bit is a one-shot bit, it is read always 0

WDTRIG

Watchdog trigger

This bit has to be toggled regularly if the watchdog is active. The watchdog can be triggered either by

this bit or by bit 0 of the configuration register.

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