L99MM70XP datasheet(17/68 Pages) STMICROELECTRONICS

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L99MM70XP

Description

Doc ID 022637 Rev 2

17/68

If bit NINTEN (CR1/Bit5, default value is set) is set, the RXD pin works also as interrupt

output in case of wake-up by LIN or INH or SPI in VCC-standby mode. This pin is pulled down

for 56 µs.

If it is not set, RXD is pulled down for 56us only for LIN wake-up.

3.6

Time-out watchdog

During normal operation, the watchdog monitors the microcontroller within a 100 ms trigger

cycle.

In VBAT-standby and flash program modes, the watchdog circuit is automatically disabled.

After power on or standby mode, the watchdog is started immediately with the normal cycle

time (100 ms). The microcontroller has to run its own setup and then to trigger the watchdog

via the SPI. The trigger is finally accepted when the CSN input becomes high after the

transmission of the SPI word.

Writing ‘1’ to the watchdog trigger bit restarts the watchdog. Subsequently, the

microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the

safe trigger area (refer to Figure 10). A correct watchdog trigger signal immediately starts

the next cycle.

If the micro does not serve the watchdog in time, the watchdog pulls low the NRES output

for 2 ms. At the same time, the watchdog failure counter (WDFAIL) is incremented by 1 and

the device enters passive mode.

After 8 watchdog failures in sequence, the VCC regulator is switched off for 200 ms. If

subsequently, 7 additional watchdog failures occur, the VCC regulator is completely turned

off and the device goes into VBAT-standby mode until a wake-up occurs.

In case of a watchdog failure, the outputs (OUTx) are switched off and the device enters

passive mode (i.e. all control registers are set to default values).

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