SI4464 datasheet(20/56 Pages) SILABS

20 / 56 page

Si4464/63/61/60

Rev 1.2

Figure 7 shows the POR timing and voltage requirements. The power consumption (battery life) depends on the

duty cycle of the application or how often the part is in either Rx or Tx state. In most applications the utilization of

the standby state will be most advantageous for battery life but for very low duty cycle applications shutdown will

have an advantage. For the fastest timing the next state can be selected in the START_RX or START_TX API

commands to minimize SPI transactions and internal MCU processing.

3.3.1. Power on Reset (POR)

A Power On Reset (POR) sequence is used to boot the device up from a fully off or shutdown state. To execute this

process, VDD must ramp within 1ms and must remain applied to the device for at least 10ms. If VDD is removed,

then it must stay below 0.15V for at least 10ms before being applied again. Please see Figure x and Table x for

details.

Figure 7. POR Timing Diagram

Table 9. Operating State Response Time and Current Consumption*

State/Mode

Response Time to

Current in State

/Mode

Shutdown State

15ms

30nA

Standby State

Sleep State

SPI Active State

Ready State

TX Tune State

RX Tune State

440 µs

340 µs

126 µs

58 µs

—

440 µs

340 µs

122 µs

—

74 µs

50 nA

900 nA

1.35 mA

1.8 mA

8mA

7.2 mA

TX State

—

138 µs

18 mA @ +10 dBm

RX State

130 µs

75 µs

10 or 13 mA

*Note:

RX and RXTX state transition timing can be reduced to 70 µs if using Zero-IF mode.

VDD

Time

VRRH

tPORH

VRRL

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