SPEAR320 datasheet(39/73 Pages) STMICROELECTRONICS

39 / 73 page

SPEAr320

Pin description

Doc ID 16755 Rev 5

39/73

Note:

Table 11 cells filled with ‘0’ or ‘1’ are unused and unless otherwise configured as Alternate

function or GPIO, the corresponding pin is held at low or high level respectively by the

internal logic.

2Pins shared by EMI and FSMC: Depending on the AHB address to be accessed the pins are

used for EMI or FSMC transfers.

PL_GPIO_1/E3

UART2_TX

IrDA_RX

GPIO_1

PL_GPIO_0/F3

UART2_RX

IrDA_TX

GPIO_0

PL_CLK1/K17

CLCP

I2C1_SDA

SD_LED

PL_CLK1

GPIO_98

PL_CLK2/J17

SD_CLK

I2C1_SCL

SD_CLK

PL_CLK2

GPIO_99

PL_CLK3/J16

SD_WP

PL_CLK3

GPIO_100

PL_CLK4/H17

SD_CMD

PL_CLK4

GPIO_101

Table 11.

PL_GPIO multiplexing scheme (continued)

PL_GPIO_# /

ball

number

Configuration mode (enabled by Programmer model

control register bits (2:0))

Alternate

function

(enabled by

RAS select

Function in

GPIO

alternative

mode

Table 12.

Table shading

Shading

Pin group

FSMC

FSMC pins: NAND Flash

EMI

EMI pins

CLCD

Color LCD controller pins

Touchscreen

Touchscreen pins

UART

UART pins

CAN

CAN pins

Ethernet MAC

MII/SMII Ethernet Mac pins

SDIO/MMC

SD card controller pins

PWM timers

Pulse-width modulator timer module pins

GPT

Timer pins

IrDa

IrDa pins

SSP

SSP pins

I2C

I2C pins

Standard Parallel port

Standard parallel port pins

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