SPEAR320 datasheet(18/73 Pages) STMICROELECTRONICS

18 / 73 page

Architecture overview

SPEAr320

18/73

Doc ID 16755 Rev 5

3.10

CAN controller

SPEAr320 has two CAN controllers for interfacing CAN 2.0 networks.

Main features:

●

Supports CAN protocol version 2.0 part A and B

●

Bit rates up to 1 MBit/s

●

16 message objects(136 X 16 message RAM)

●

Each message object has its own identifier mask

●

Maskable interrupt

●

Programmable loop-back mode for self-test operation

●

Disabled automatic retransmission mode for time triggered CAN applications

3.11

USB2 Host controller

SPEAr320 has two fully independent USB 2.0 Hosts. Each consists of 5 major blocks:

●

EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)

●

OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)

●

Local 2-Kbyte FIFO

●

Local DMA

●

Integrated USB2 transceiver (PHY)

Both Hosts can manage an external power switch, providing a control line to enable or

disable the power, and an input line to sense any over-current condition detected by the

external switch.

One Host controller at time can perform high speed transfer.

3.12

USB2 Device controller

Main features:

●

Supports the 480 Mbps high-speed mode (HS) for USB 2.0, as well as the 12 Mbps

full-speed (FS) and the low-speed (LS modes) for USB 1.1

●

Supports 16 physical endpoints, configurable as different logical endpoints

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Integrated USB transceiver (PHY)

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Local 4 Kbyte FIFO shared among all the endpoints

●

DMA mode and slave-only mode are supported

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In DMA mode, the UDC supports descriptor-based memory structures in application

memory

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In both modes, an AHB slave is provided by UDC-AHB, acting as programming

interface to access to memory-mapped control and status registers (CSRs)

●

An AHB master for data transfer to system memory is provided, supporting 8, 16, and

32-bit wide data transactions on the AHB bus

●

A USB plug (UPD) detects the connection of a cable.

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