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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SPEAR320 Fiches technique(PDF) 36 Page - STMicroelectronics |
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SPEAR320 Fiches technique(HTML) 36 Page - STMicroelectronics |
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36 / 73 page  Pin description SPEAr320 36/73 Doc ID 16755 Rev 5 PL_GPIO_86/E17 CLD11 MII1_RXD1 EMI_A11 0 GPIO_86 PL_GPIO_85/F15 CLD12 MII1_RXD2 EMI_A12 SPP_DATA0 GPIO_85 PL_GPIO_84/D17 CLD13 MII1_RXD3 EMI_A13 SPP_DATA1 GPIO_84 PL_GPIO_83/E16 CLD14 MII1_COL EMI_A14 SPP_DATA2 GPIO_83 PL_GPIO_82/E15 CLD15 MII1_CRS EMI_A15 SPP_DATA3 GPIO_82 PL_GPIO_81/C17 CLD16 MII1_MDIO EMI_A16 SPP_DATA4 GPIO_81 PL_GPIO_80/D16 CLD17 MII1_MDC EMI_A17 SPP_DATA5 GPIO_80 PL_GPIO_79/F14 CLD18 0 EMI_A18 SPP_DATA6 GPIO_79 PL_GPIO_78/D15 CLD19 0 EMI_A19 SPP_DATA7 GPIO_78 PL_GPIO_77/B17 CLD20 0 EMI_A20 SPP_STRBn GPIO_77 PL_GPIO_76/F13 CLD21 0 EMI_A21 SPP_ACKn GPIO_76 PL_GPIO_75/E14 CLD22 0 EMI_A22 SPP_BUSY GPIO_75 PL_GPIO_74/C16 CLD23 0 EMI_A23 SPP_PERROR GPIO_74 PL_GPIO_73/A17 CLAC 0 EMI_D8/ FSMC_D8 SPP_SELECT GPIO_73 PL_GPIO_72/B16 CLFP 0 EMI_D9/ FSMC_D9 SPP_AUTOFDn GPIO_72 PL_GPIO_71/D14 CLLP 0 EMI_D10/ FSMC_D10 SPP_FAULTn GPIO_71 PL_GPIO_70/C15 CLLE 0 EMI_D11/ FSMC_D11 SPP_INITn GPIO_70 PL_GPIO_69/A16 CLPOWER 0 EMI_WAIT SPP_SELINn GPIO_69 PL_GPIO_68/B15 FSMC_D0 FSMC_D0 EMI_D0/ FSMC_D0 FSMC_D0 GPIO_68 PL_GPIO_67/C14 FSMC_D1 FSMC_D1 EMI_D1/ FSMC_D0 FSMC_D1 GPIO_67 PL_GPIO_66/E13 FSMC_D2 FSMC_D2 EMI_D2/ FSMC_D2 FSMC_D2 GPIO_66 PL_GPIO_65/B14 FSMC_D3 FSMC_D3 EMI_D3/ FSMC_D3 FSMC_D3 GPIO_65 PL_GPIO_64/D13 FSMC_D4 FSMC_D4 EMI_D4/ FSMC_D4 FSMC_D4 GPIO_64 PL_GPIO_63/C13 FSMC_D5 FSMC_D5 EMI_D5/ FSMC_D5 FSMC_D5 GPIO_63 PL_GPIO_62/A15 FSMC_D6 FSMC_D6 EMI_D6/ FSMC_D6 FSMC_D6 H7 GPIO_62 PL_GPIO_61/E12 FSMC_D7 FSMC_D7 EMI_D7/ FSMC_D7 FSMC_D7 H6 GPIO_61 PL_GPIO_60/A14 FSMC_ADDR_L E FSMC_ADDR_L E FSMC_ADDR_LE FSMC_ADDR_LE H5 GPIO_60 PL_GPIO_59/B13 FSMC_WE FSMC_WE EMI_WE/ FSMC_WE FSMC_WE H4 GPIO_59 PL_GPIO_58/D12 FSMC_RE FSMC_RE EMI_OE/ FSMC_RE FSMC_RE H3 GPIO_58 Table 11. PL_GPIO multiplexing scheme (continued) PL_GPIO_# / ball number Configuration mode (enabled by Programmer model control register bits (2:0)) Alternate function (enabled by RAS select register) Function in GPIO alternative mode 12 3 4 |
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