SPEAR320 datasheet(22/73 Pages) STMICROELECTRONICS

22 / 73 page

Architecture overview

SPEAr320

22/73

Doc ID 16755 Rev 5

Main features:

●

Compliance with the baseline JPEG standard (ISO/IEC 10918-1)

●

Single-clock per pixel encoding/decoding

●

Support for up to four channels of component color

●

8-bit/channel pixel depths

●

Programmable quantization tables (up to four)

●

Programmable Huffman tables (two AC and two DC)

●

Programmable minimum coded unit (MCU)

●

Configurable JPEG header processing

●

Support for restart marker insertion

●

Use of two DMA channels and of two 8 x 32-bits FIFO's (local to the JPEG) for efficient

transferring and buffering of encoded/decoded data from/to the CODEC core.

3.20

Cryptographic co-processor (C3)

SPEAr320 has an embedded Channel Control Coprocessor (C3). C3 is a high-performance

instruction driven DMA based co-processor. It executes instruction flows generated by the

host processor. After it has been set-up by the host it runs in a completely autonomous way

(DMA data in, data processing, DMA data out), until the completion of all the requested

operations.

C3 has been used to accelerate the processing of cryptographic, security and network

security applications. It can be used for other types of data intensive applications as well.

Main features:

●

Supported cryptographic algorithms:

–

Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes.

–

Data encryption standard (DES) cipher in ECB and CBC modes.

–

SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.

●

Instruction driven DMA based programmable engine.

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AHB master port for data access from/to system memory.

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AHB slave port for co-processor register accesses and initial engine-setup.

●

The co-processor is fully autonomous (DMA input reading, cryptographic operation

execution, DMA output writing) after being set up by the host processor.

●

The co-processor executes programs written by the host in memory, it can execute an

unlimited list of programs.

●

The co-processor supports hardware chaining of cryptographic blocks for optimized

execution of data-flow requiring multiple algorithms processing over the same set of

data (for example encryption + hashing on the fly).

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