L99UDL01 datasheet(14/88 Pages) STMICROELECTRONICS

14 / 88 page

Device description

L99UDL01

14/88

DS12511 Rev 5

Device description

2.1

Overview

The L99UDL01 is a 6+2 channel half bridge driver monolithic integrated circuit designed to

power a centralized door lock system. This device is made possible by the incorporation of

current regulated drivers limiting the current in the door lock motors to a preset level (for

example the current levels seen at a 9 V battery).

The current is regulated by controlling the PWM duty cycle at a programmed frequency.

2.2

Supply monitoring

2.2.1

Low Voltage Inhibit (VSLVI)

The Vs supply has a low voltage warning function with hysteresis. When Vs drops below

VSLVI_F the outputs (internal half bridges and drivers for external MOSFET) are disabled

and the VSLVI bit is set in register 12H (the SPI diagnostic register).

Once Vs rises above the rising VSLVI_R threshold the outputs are re-enabled and ready for

use. Actuation can be restarted via SPI frame or EN_OUT rising edge according to

configuration registers. The VSLVI bit remains set in the SPI diagnostic register and is

cleared only upon read & clear.

2.2.2

Overvoltage (VSOVSD)

When VS rises above VSOVSD the outputs (internal half bridges and drivers for external

MOSFETs) are disabled and the VOVSD bit is set in the SPI diagnostic register.

Once VS falls below VSOVSD the outputs are re-enabled and ready for use. Actuation can

be restarted according to configuration registers via SPI frame or EN_OUT rising edge. The

VSOVSD bit (diagnostic register 12H) remains set until read & clear SPI frame.

2.2.3

VDD monitoring

The VDD pin (5 V/3.3 V) is a supply pin for the L99UDL01 I/O. This pin is monitored by 2

under voltage conditions. In case of an undervoltage condition during Normal mode (VDD <

VDDUV) the device will enter into stand-by mode and all of the control registers will be reset

to their default values after tVDDUV. In case of an undervoltage condition (VDD<VDDSLEEP),

the device enters into the ultra-low quiescent sleep mode and the internal regulator is

disabled. CSN must be held high while VDD falls below

VDDSLEEP to ensure the L99UDL01

enters into sleep mode.

Upon rising out of VDDSLEEP the device will perform a power-on reset and enter into

Standby mode until a CSN wake-up has occurred. The reset (RSTB) bit will remain set until

the first SPI communication.

2.2.4

3V3 monitoring

The internal 3.3 V regulator, 3V3, is monitored for under voltage conditions to ensure the

logic integrity.

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