L99UDL01 datasheet(72/88 Pages) STMICROELECTRONICS

72 / 88 page

Programmers guide

L99UDL01

72/88

DS12511 Rev 5

STBY2

Standby is entered when bit 13 in this register and bit 13 in register 06H are set in order.

First STBY1 must be set and then STBY2 must be set for standby to be initiated. Upon the

rising edge of CSN, when setting the second of the two bits, the device will enter standby.

Setting only one of the bits or setting the bits out of order will not cause the device to enter

standby.

Once entering Standby no communication can occur without waking the device up (CSN

falling edge)

6.2.6

This register provides the option of adjusting the control loop P-I parameters. These

parameters are set to a typical default setting that will fit most applications.

This register can be read or written to. All new data programmed into this register will be

acted upon the rising edge of CSN even during a timed actuation.

Figure 24. 08H Current regulation loop control register

OC1

OC2

D 15 D 14 D 13 D 12 D 11 D 10

D 9

D 8

D 7

D 6

D 5

D 4

D 3D 2

D 1D 0

001000

Reserved

Default Values

0000000001

01101

Table 47. 08H Register bit description

Bit No.

Function

Level

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

KI_2

Integral gain of regulation loop bit 2

KI_1

Integral gain of regulation loop bit 1

KI_0

Integral gain of regulation loop bit 0

KP_2

Proportional gain of regulation loop bit 2

KP_1

Proportional gain of regulation loop bit 1

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