L99UDL01 datasheet(78/88 Pages) STMICROELECTRONICS

78 / 88 page

Programmers guide

L99UDL01

78/88

DS12511 Rev 5

Due to the nature of the active freewheeling, a short across the regulated switch may show

up as a CNR. It is recommended that if a CNR is detected that an off-state load diagnostic

be performed using the dynamic output voltage detect (DOSx Register 11H) with the weak

pull-up/down currents (ODCxy in register 07H).

A PWM controlled output may not detect a shorted driving element. The output current may

be read or an off state load diagnostic may be performed to verify the load integrity.

For grouped outputs only the Master status bits (OUT1 or OUT 4) contain the correct fault

information for their respective groups. Slave status bits may be ignored.

It is recommended that all of the status bits, single or paralleled, be completely cleared to

guarantee proper operation.

RD_Fail

If a read command is given for a register that is non-existent a read fail bit will be set. The

SPIE bit in the global status byte will also be set. There will be no effect on the function of

the IC as a result of a Read Fail event. The data will be ignored.

SPI_Fail

A SPI Fail bit is set if the clock count is incorrect or the SDI pin is stuck high or low or if a

parity error is detected. A clock count error occurs when the clock count between the falling

and rising edge of the CSN pin is not 24 (not burst read mode). For a SPI Burst Read the

SPI Data Length plus multiple numbers of Payload SCK edges are assumed as a valid

communication (e.g. 8+ n x 16 where n = the number of additional payloads read). Anything

outside of that count would be considered a SPI Fail.

A SPI failure does not change the behavior of the device. That is, if a SPI fail occurs no

registers will change their value as a result of that attempted SPI transmission.

WRT_Fail

A write fail occurs if incorrect data is written to an existing command or configuration register

(06H-07H). The data will be transferred to the register and the WRT_Fail flag will be set and

latched until the correct data is written followed by a read and clear command. A write fail

can also occur if the address used is not one of the command or configuration registers

(00H – 09H).

Table 53. Output status bit description

Output diagnostic

FLTx_1

FLTx_0

Diagnostic

No Fault

Overcurrent

CNR

Not used

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