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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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L9300 Fiches technique(PDF) 97 Page - STMicroelectronics |
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L9300 Fiches technique(HTML) 97 Page - STMicroelectronics |
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97 / 178 page  16.1.1 SPI protocol The SPI protocol is defined by frames of 32 bit with 3 bit of CRC (Cyclic Redundancy Check) both input and output directions. SDI frame includes 7 bit address and 20 bit data, SDO frame includes channel exception field for diagnostic status immediate capture. SPI implements In-Frame protocol for data out management. 16.1.2 CRC field UAL3 SPI frame (upstream/downstream) include a 3 bit CRC field. CRC field is evaluated/checked by using 3° degree poly G3(x) = x3+x+1. In case CRC error is detected the fault is output in the following SPI frame, if the CRC fault is flagged it means the previous frame is considered invalid and no write operation or clear operation is performed. 16.1.3 Channel exception field details SDO frame has 6 bits reserved for solenoid channel exceptions, each bit is dedicated to the corresponding channel and it is the OR of all the recorded exceptions. In this way, it is always possible to detect a failure happening on each solenoid channel during every SPI communication; details and clearing of the channel exception can be retrieved reading the dedicated SPI registers. In case a fault happens during reading operation of its own fault register it is not latched, however if the fault is permanent it is latched as soon as the reading operation has ended. 16.2 SPI electrical characteristics 5.5 V ≤ VBATP ≤ 19 V; 3.1 V < VDDIO < 5.2 V; -40 °C ≤ Tj ≤ 175 °C unless otherwise noticed. All voltages refer to GND pin. Table 55. SPI electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Pin DC Parameters VDDIO SPI Dedicated Power Supply Application note 3.0 5.5 V VDDIO VIL Logic Input Low Voltage - 0.75 V SCLK VIH Logic Input High Voltage 1.75 - V SCLK Vhysteresis Input hysteresis Voltage 0.1 1 V SCLK SCLKPD SCLK pull-down SCLK = 5V 10 50 100 µA SCLK VIL Logic Input Low Voltage - 0.75 V SDI VIH Logic Input High Voltage 1.75 - V SDI Vhysteresis Input hysteresis Voltage 0.1 1 V SDI SDIPD SDI pull-down SDI = 5V 10 50 100 µA SDI VIL Logic Input Low Voltage - 0.75 V CS VIH Logic Input High Voltage 1.75 - V CS Vhysteresis Input hysteresis Voltage 0.1 1 V CS CSPU CS pull-up to internal logic supply CS = 0V 10 30 60 µA CS VOL Logic Output Low Voltage Isource = 1mA 0.4 V SDO VOH Logic Output High Voltage Isink = 1mA VDDIO-0.4 V SDO Ileak Tristate leakage current CS high 0<SDO<VDDIO -0.5 0.5 µA SDO AC Parameters fop Transfer Frequency Design Information 6 MHz SCLK tsclk SCLK Period (2) Design Information 167 ns SCLK L9300 SPI interface and register mapping DS12258 - Rev 5 page 97/178 |
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