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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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L9300 Fiches technique(PDF) 18 Page - STMicroelectronics |
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L9300 Fiches technique(HTML) 18 Page - STMicroelectronics |
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18 / 178 page  7.6 Power up/down electrical characteristics 5.5V ≤ VBATP ≤ 19V; -40°C ≤ Tj ≤ 175°C unless otherwise noticed. All voltages referred to GND pin. Table 5. Power up/down electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Pin Current Consumption VBATP_stby_cur VBATP stby current consumption WAKE=0V, VBATP, PD1D, VDD4_SH, VDD4_SL, VDD2_SUP, VSx=13V CONFIG=0V Tambient <= 70°C 5 45 µA VBATP VBATP_stby_cur VBATP stby current consumption WAKE=0V, VBATP, PD1D, VDD4_SH, VDD4_SL, VDD2_SUP, VSx=13V, CONFIG=13V 20 90 µA VBATP VBATP_cur VBATP ON current cunsumption VBATP = 13V, WAKE=HIGH 20 30 75 mA VBATP Wake Up WAKE_high_th WAKE high threshold 2.7 3.5 V WAKE WAKE_low_th WAKE low threshold 2 2.7 V WAKE WAKE_hys WAKE hysteresis 0.5 V WAKE WAKE_pd WAKE pull down WAKE < WAKE_high_th 0.4 2 MΩ WAKE CONFIG_low Low current mode 0.75 V CONFIG CONFIG_high Full functionality mode 1.75 V CONFIG VDD_st_en Supply start enable 4.3 4.5 4.7 V VDD1 VDD_st_en_deglitch Digital filter time Guaranteed by scan 7.5 10 12.5 µs VDD1 Tmask_VDD2_SEL Masking of VDD2 enable signal (after VDD3/4_uv release) Guaranteed by scan 150 200 250 µs VDD2_SEL Tdelay_VDD2 Analog delay on soft start ramp 100 700 µs VDD2 Tmask_TRK_SEL Masking of TRKn enable signal (after VDD3/4_uv release) Guaranteed by scan 150 200 250 µs TRK_SEL Tdelay_TRKn Analog delay on soft start ramp 100 700 µs TRKn WK_FLT_up Wake up deglitch Guaranteed by scan 7.5 10 12.5 µs WAKE WK_FLT_down Wake up deglitch Guaranteed by scan 7.5 10 12.5 µs WAKE WAKE_tmin Wake high minimum time to power-on internal logic Design info, guaranteed by design 150 µs WAKE Keep On KA_period Keep-alive period Guaranteed by scan 180 200 220 ms WAKE VDD3_dly Delay VDD3 from VDD4 at power up Guaranteed by scan 0.8 1 1.2 ms VDD3/4 Power Down VDD4_dly Delay VDD4 from VDD3 at power down Guaranteed by scan 23 35 µs VDD3/4 L9300 Power up and power down DS12258 - Rev 5 page 18/178 |
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