L9300 datasheet(90/178 Pages) STMICROELECTRONICS

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CAN Interface

15.1

CAN interface functional description

The CAN interface main features are the following:

•

Compatible to the ISO 11898-2 standard

•

Communication speed up to 1 Mbit/s

•

Function range from -18 V to +40 V DC at CAN pins

•

GND disconnection fail safe at module level

•

GND shift operation at system level

•

Microcontroller interface with CMOS compatible I/O Pins.

•

Matched output slopes and propagation delay

•

Receive-only mode available

In order to further reduce the current consumption in standby mode, the integrated CAN bus interface offers an

ultra low current consumption.

15.1.1

CAN error handling

At V33_DIG > POR threshold (internal power on reset), the CAN transceiver is enabled. CAN transmitter is

supplied by a dedicated pin (CANVDD) to avoid disturbances of CAN activity on main supply lines. The CAN

transmitter is disabled only in case of the following errors:

•

Dominant TxDC timeout

•

CAN permanent recessive

•

RxDC permanent recessive

•

Thermal shutdown TSD_VDD1

•

WD reset

The CAN receiver is not disabled in case of any failure condition.The device provides the following 4 error

handling features; the CAN error handling function can be disabled by setting a proper SPI bit.

Dominant TxDC Timeout

If TXDC is in dominant state (low) for t > tTXDC_DOM_TO the transmitter is disabled, status bit is latched and

cleared by SPI read. The transmitter remains disabled until the status register is cleared.

CAN Permanent Recessive

If TXDC changes to dominant (low) state but CAN bus does not follow for 4 times, the transmitter is disabled,

status bit is latched and cleared by SPI read. The transmitter remains disabled until the status register is cleared.

CAN Permanent Dominant

If the bus state is dominant (low) for t > tCAN_DOM_TO a permanent dominant status is detected. The status bit is

latched and cleared by SPI read. The transmitter is not disabled.

RXDC Permanent Recessive

If RXDC Pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and

could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RXDC

does not follow TXDC for 4 times the transmitter is disabled. The status bit is latched and can be cleared by SPI

read. The transmitter remains disabled until the status register is cleared.

15.1.2

Wakeup (from CAN)

When the device is in standby mode, with CAN wake up option enabled, the CAN bus traffic is detected. For the

wake up feature the device logic differentiates different conditions. When the device is in standby mode, with CAN

wake up option enabled, the CAN bus traffic is detected. For the wake up feature the device logic differentiates

between the following conditions.

L9300

CAN Interface

DS12258 - Rev 5

page 90/178

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