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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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L9300 Fiches technique(PDF) 28 Page - STMicroelectronics |
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L9300 Fiches technique(HTML) 28 Page - STMicroelectronics |
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28 / 178 page  Table 12. VDD4 electrical characteristics Symbol Parameter Test condition Min Typ Max Unit Pin Configuration Input VIL Logic Input Low Voltage - 0.75 V VDD4_SH VIH Logic Input High Voltage 1.75 - V VDD4_SH Vhysteresis Input hysteresis Voltage 0.1 1 V VDD4_SH Ileak_VDD4_SH Leakage current VDD4_SH = 13 V, WAKE=0 V -1 1 µA VDD4_SH Ileak_VDD4_SL Leakage current VDD4_SL = 13 V, WAKE=0 V -1 1 µA VDD4_SL VDD4_SHPD VDD4_SH pull down VDD4_SH = 5 V 10 50 100 µA VDD4_SH Linear Configuration Ciss External FET input capacitor Application note: FET selection max input capacitance to guarantee stability 900 pF Gm External FET transconductance Application note: FET selection 20 mho Vth External FET threshold Application note: FET selection threshold voltage 3 V VDD4_Vout Output voltage Application note 0.8 5 V VDD4 IVDD4 Output load current Application note 0.01 1 A VDD4 CVDD4 Output capacitor Application note 5 40 µF VDD4 CVDD4_OPT Optional output capacitor(1) Application note: max drivable cap in parallel with CVDD4 200 µF VDD4 CVDD4 ESR Output capacitor ESR Application note f <= 150 kHz 0.01 0,1 Ω VDD4 CDRAIN3 EMI Drain Output capacitor Application note, VDRAIN=VBATP, capacitor required on the drain of external N-ch FET to prevent selfmode oscillations and to improve EMI robustness 1 µF CDRAIN3 EMI Drain Output capacitor Application note, VDRAIN=VDD1, capacitor required on the drain of external N-ch FET to prevent selfmode oscillations and to improve EMI robustness 0.1 µF R4up Feedback resistor range Application note 5 15 kΩ VDD4_SEL VDD4_SEL Regulated feedback voltage 0.01 A ≤ IVDD3 ≤ 1 A 0.8 – 2% 0.8 0.8 + 2% V VDD4_SEL VDD4_SEL line Line regulation VDRAIN 6 V to 19 V, IVDD4 = 0.01 A, 1 A -5 +5 mV VDD4_SEL VDD4_SEL load Load regulation IVDD4 = 0.01 A to 1 A, VDRAIN 6 V to 19 V -5 +5 mV VDD4_SEL VDD4_SEL _tr1 Transient output voltage 1 VDRAIN = 13 V, VDD4 ≥ 3.3 V, ∆IVDD4 =300 mA; dI/dt = 0.5 A/µs, CVDD4 = 5 µF, Guaranteed by design -5 +5 % VDD4_SEL VDD4_SEL _tr1 Transient output voltage 1 (No Reset Asserted) VDRAIN = 13 V, VDD4 < 3.3 V, ∆IVDD4 =300 mA; dI/dt = 0.5 A/µs, CVDD4 = 5 µF, Guaranteed by design -8 +8 % VDD4_SEL VDD4_SEL _tr2 Transient output voltage 2 (No Reset Asserted) VDRAIN step 12 V to 18 V; 18 V to 12 V, dVDRAIN/dt = 3 V/µs, IVDD4 = 0.01 A, 1 A, CVDD4 = 5 µF, Guaranteed by design -7 +7 % VDD4_SEL L9300 Power supply DS12258 - Rev 5 page 28/178 |
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