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AM186 Fiches technique(PDF) 100 Page - Advanced Micro Devices |
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AM186 Fiches technique(HTML) 100 Page - Advanced Micro Devices |
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100 / 112 page ![]() 100 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Reset Waveforms Signals Related to Reset Waveforms X1 RES CLKOUTA 57 57 Note: RES must be held Low for 1 ms during power-up to ensure proper device initialization. Activating the PLL will require 1 ms to achieve a stable clock. BHE/ADEN*, RFSH2/ADEN*, S6/CLKSEL1* **, UZI/CLKSEL2** S1/IMDIS*, and S0/SREN* RES CLKOUTA AD15–AD0 (186) AO15–AO8, AD7–AD0 (188) Notes: * Because BHE, RFSH2, S6, UZI, S1, and S0 are not driven for 6.5 clocks after reset, their alternate functions can be asserted with external pulldown resistors. ** In Divide by Two mode and Times One mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 3 clock cycles after reset negates. ***In Times Four mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 5 clock cycles after reset negates. S6/CLKSEL1***, UZI/CLKSEL2*** Three-State Three-State Divide by Two and Times One Modes Times Four Mode Three-State |
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