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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM186 Fiches technique(PDF) 70 Page - Advanced Micro Devices |
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AM186 Fiches technique(HTML) 70 Page - Advanced Micro Devices |
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70 / 112 page  70 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle (25 MHz and 33 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Preliminary Parameter 25 MHz 33 MHz No. Symbol Description Min Max Min Max Unit General Timing Requirements 1 tDVCL Data in Setup 10 8 ns 2 tCLDX Data in Hold(c) 3 3 ns General Timing Responses 3 tCHSV Status Active Delay 0 20 0 15 ns 4 tCLSH Status Inactive Delay 0 20 0 15 ns 5 tCLAV AD Address Valid Delay 0 20 0 15 ns 7 tCLDV Data Valid Delay 0 20 0 15 ns 8 tCHDX Status Hold Time 0 0 ns 9 tCHLH ALE Active Delay 20 15 ns 10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns 11 tCHLL ALE Inactive Delay 20 15 ns 12 tAVLL AD Address Valid to ALE Low(a) tCLCH tCLCH ns 13 tLLAX AD Address Hold from ALE Inactive(a) tCHCL tCHCL ns 14 tAVCH AD Address Valid to Clock High 0 0 ns 15 tCLAZ AD Address Float Delay tCLAX=0 20 tCLAX=0 15 ns 16 tCLCSV MCS/PCS Active Delay 0 20 0 15 ns 17 tCXCSX MCS/PCS Hold from Command Inactive(a) tCLCH tCLCH ns 18 tCHCSX MCS/PCS Inactive Delay 0 20 0 15 ns 19 tDXDL DEN Inactive to DT/R Low(a) 0 0 ns 20 tCVCTV Control Active Delay 1(b) 0 20 0 15 ns 21 tCVDEX DEN Inactive Delay 0 20 0 15 ns 22 tCHCTV Control Active Delay 2(b) 0 20 0 15 ns 23 tLHAV ALE High to Address Valid 15 10 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 0 ns 25 tCLRL RD Active Delay 0 20 0 15 ns 26 tRLRH RD Pulse Width 2tCLCL–15=65 2tCLCL–15=45 ns 27 tCLRH RD Inactive Delay 0 20 0 15 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns 29 tRHAV RD Inactive to AD Address Active(a) tCLCL–10=30 tCLCL–10=20 ns 59 tRHDX RD High to Data Hold on AD Bus(c) 0 0 ns 66 tAVRL A Address Valid to RD Low 2tCLCL–15=65 2tCLCL–15=45 ns 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 20 0 15 ns 68 tCHAV CLKOUTA High to A Address Valid 0 20 0 15 ns |
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